iverilog

TimRudy/ice-chips-verilog

IceChips is a library of all common discrete logic devices in Verilog

ashishrana160796/verilog-starter-tutorials

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

TheSUPERCD/8bit_MicroComputer_Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

sgherbst/svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

JeffDeCola/my-verilog-examples

A place to keep my synthesizable verilog examples.

TimRudy/uart-verilog

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

Essenceia/ethernet-physical-layer

RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

maazm007/vsdsquadron-mini-internship

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

yasnakateb/PipelinedARM

💎 A 32-bit ARM Processor Implementation in Verilog HDL

OpenEDF/verilog-basic

learn the combinational and sequential logic circuit.

patrickleboutillier/jcscpu-hw

Hardware implementation, using a Digilent Basys-3 FPGA board, of the computer described in J. Clark Scott's book "But How Do It Know?".

pangguoming/iview-admin

Vue 2.0 admin management system template based on iView 个人修改版

yasnakateb/NoCRouter

🎞️ NoC router in Verilog with FIFO

jfcherng-sublime/SublimeLinter-contrib-iverilog

This linter plugin for SublimeLinter provides an interface to iverilog (verilog compiler).

KiranThomasCherian/VLSI-and-Computer-Architecture

Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim

lib3yu/fft_verilog

使用verilog实现流水线 FFT

pytec8800/pint_iverilog

Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.

dpretet/meduram

Multi-port BRAM IP for ASIC and FPGA

johnnycubides/digital-electronic-1-101

rodrigomelo9/verifying-foss-hdl-synthesizers

a project to check the FOSS synthesizers against vendors EDA tools

yasnakateb/PipelinedMIPS

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

a2k-hanlon/linter-veriloghdl

Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.

BestDreamy/aricriscv

5-pipe core for RISCV32I

NAvi349/rtl-sky130-ws

This is a documentation of the work done as part of the 5 - day RTL Design Workshop using Verilog with SKY130 Technology

strongwong/bittyCore_RISC-V

This is a bitty CPU core of risc-v architecture, which is currently under development.

arjunrajasekharan/16-bit-DADDA-Multiplier

16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.

arjunrajasekharan/16bit-Sklansky-Adder

16-bit Slansky Adder design using verilog HDL

ArvinDelavari/Digital-Circuits-Verilog

Sample Verilog codes for digital circuits

yasnakateb/AES

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL

yasnakateb/UARTCommunication

☎️ UART Communication Implementation in Verilog HDL

mshr-h/fibonacci_verilog

fibonacci number calculator written in Verilog-HDL

superphosphate/verilog-with-iverilog-gtkwave

A Visual Studio Code extension for compiling Verilog modules with Iverilog and simulating results with GTKWave.

yasnakateb/SdramController

🛠 A SDRAM controller in Verilog HDL

ErickMaRi/Proyecto-Digitales-II

Diseño de un par controlador-periférico según el protocolo MDIO (cláusula 22)

Prawinkumarjs/VSDSquadron-mini-internship

Internship at VSD on RISC-V and VLSI using VSDSquadron Mini Board