uart-verilog
There are 31 repositories under uart-verilog topic.
pConst/basic_verilog
Must-have verilog systemverilog modules
ZipCPU/wbuart32
A simple, basic, formally verified UART controller
ben-marshall/uart
A simple implementation of a UART modem in Verilog.
halftop/Interface-Protocol-in-Verilog
Interface Protocol in Verilog
TimRudy/uart-verilog
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
GLADICOS/UART
This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog
addisonElliott/LogiFindFPGATest
This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.
yasnakateb/UARTCommunication
☎️ UART Communication Implementation in Verilog HDL
Shubhayu-Das/VL504-project
Displaying images taken from an OV7670/laptop camera
KelvinThomasYB17/Transferring-data-from-SPI-to-UART-using-BMP280-sensor-with-Verilog
Transferring data from SPI to UART using BMP280 sensor with Verilog
mwbryant/uart-CI
Basic continous integration testing for verilog projects
TheLeopardsH/UART
Universal Asynchronous Receiver Transmitter
Wissance/QuickRS232
A versatile full-duplex RS232 FPGA module with internal FIFO buffer on RX
BrunoBMoura/BM_CORE
Single-cycle MIPS-based processor architecture, designed as the final project for the Laboratory of Computer Architecture and Organization course and later enhanced for both Laboratory of Operational Systems and Laboratory of Computer Networks courses.
ColtonBeery/UART_TX
Basys 3 UART Tx for COMPE470L class
djkabutar/test_mipi_encoder_decoder
MIPI to multiple peripheral (UART, I2C, SPI, 1-Wire)
Fahad-Habib/UART-Tx
UART Tx implemented in SystemVerilog from scratch.
KevinWang96/UART_Verilog_Based
Verilog Modeling of UART Tx and Rx
sidhantp1906/UART
UART implementation using Verilog HDL
STjurny/BasicUART
Small light-weight implementation of UART in Verilog.
2uger/verilog_uart_hw
Verilog UART implementation with Vivado build scripts to test loopback on Xilinx Arty board
Abd-El-Rahman-Sabry/processing-unit-with-uart
This project implements a UART-controlled processing unit with dual clock domains for UART communication and datapath operations. A state machine decodes serial commands to control the datapath, enabling ALU operations, register file access, and data transmission. It's designed for embedded systems and educational purposes.
hl271/uart_with_fifo
Verilog implementation of UART protocol with integrated FIFO buffer
PhatLe15/Computer-Architecture-Design
Pipelining and timing issues in CPU data-paths. Principles of RISC-type CPU instruction set and architecture. Structural, data and control hazards in a RISC processor, forwarding loops, branch mechanisms. Memory architectures in CPUs such as register files and caches. UART, I2C protocols.
sushi0706/uart
verilog-uart
0marAmr/UART-Interface
Design of Universal Asynchronous Receiver Transmitter Interface using verilog HDL
mengstr/vuart
WIP - Smallish UART written in Verilog
MohamedHussein27/UART-With-FIFOs
This repository contains the Verilog implementation of a UART protocol with FIFOs for handling data transmission and reception
TahirZia-1/UART
A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.