uart-verilog

There are 36 repositories under uart-verilog topic.

  • pConst/basic_verilog

    Must-have verilog systemverilog modules

    Language:Verilog1.9k585411

  • ZipCPU/wbuart32

    A simple, basic, formally verified UART controller

    Language:Verilog31416350

  • ben-marshall/uart

    A simple implementation of a UART modem in Verilog.

    Language:Verilog1643625

  • halftop/Interface-Protocol-in-Verilog

    Interface Protocol in Verilog

    Language:Verilog504120

  • TimRudy/uart-verilog

    A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

    Language:Verilog36204

  • GLADICOS/UART

    This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog

    Language:Verilog7302

  • addisonElliott/LogiFindFPGATest

    This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.

    Language:Verilog6203

  • yasnakateb/UARTCommunication

    ☎️ UART Communication Implementation in Verilog HDL

    Language:Verilog5100

  • kishanpatelec/UART-for-bluetooth-module

    Language:Verilog4100

  • Shubhayu-Das/VL504-project

    Displaying images taken from an OV7670/laptop camera

    Language:Python3100

  • AhmedSobhy01/uart-verilog

    Synthesizable Verilog implementation of the classic UART 16550 serial interface implements configurable baud rate, FIFO buffering, parity, error detection, and testbenches for simulation

    Language:Verilog2

  • KelvinThomasYB17/Transferring-data-from-SPI-to-UART-using-BMP280-sensor-with-Verilog

    Transferring data from SPI to UART using BMP280 sensor with Verilog

    Language:Verilog2100

  • KevinWang96/UART_Verilog_Based

    Verilog Modeling of UART Tx and Rx

    Language:Verilog2100

  • mwbryant/uart-CI

    Basic continous integration testing for verilog projects

    Language:C++210

  • TheLeopardsH/UART

    Universal Asynchronous Receiver Transmitter

    Language:Verilog2100

  • Wissance/QuickRS232

    A versatile full-duplex RS232 FPGA module with internal FIFO buffer on RX

    Language:Verilog2311

  • Abd-El-Rahman-Sabry/processing-unit-with-uart

    This project implements a UART-controlled processing unit with dual clock domains for UART communication and datapath operations. A state machine decodes serial commands to control the datapath, enabling ALU operations, register file access, and data transmission. It's designed for embedded systems and educational purposes.

    Language:Verilog1100

  • BrunoBMoura/BM_CORE

    Single-cycle MIPS-based processor architecture, designed as the final project for the Laboratory of Computer Architecture and Organization course and later enhanced for both Laboratory of Operational Systems and Laboratory of Computer Networks courses.

    Language:Verilog1001

  • ColtonBeery/UART_TX

    Basys 3 UART Tx for COMPE470L class

    Language:Verilog1100

  • djkabutar/test_mipi_encoder_decoder

    MIPI to multiple peripheral (UART, I2C, SPI, 1-Wire)

    Language:Verilog1101

  • Fahad-Habib/UART-Tx

    UART Tx implemented in SystemVerilog from scratch.

    Language:SystemVerilog1100

  • meeeeet/UART-DesignAndVerification

    Language:SystemVerilog1100

  • sidhantp1906/UART

    UART implementation using Verilog HDL

    Language:Verilog1100

  • STjurny/BasicUART

    Small light-weight implementation of UART in Verilog.

    Language:Verilog1101

  • 2uger/verilog_uart_hw

    Verilog UART implementation with Vivado build scripts to test loopback on Xilinx Arty board

    Language:Python0100

  • fscatox/efes_prj

    FPGA + STM32 stepper motor controller with programmable movement pattern, PS/2 keyboard interface, and non-volatile pattern storage. Toy system developed for the "Electronics for Embedded Systems" course at PoliTO

    Language:C++00

  • hl271/uart_with_fifo

    Verilog implementation of UART protocol with integrated FIFO buffer

    Language:Verilog0101

  • PhatLe15/Computer-Architecture-Design

    Pipelining and timing issues in CPU data-paths. Principles of RISC-type CPU instruction set and architecture. Structural, data and control hazards in a RISC processor, forwarding loops, branch mechanisms. Memory architectures in CPUs such as register files and caches. UART, I2C protocols.

    Language:HTML0100

  • sushi0706/uart

    verilog-uart

    Language:Verilog0100

  • 0marAmr/UART-Interface

    Design of Universal Asynchronous Receiver Transmitter Interface using verilog HDL

    Language:Verilog10

  • DatNT018/FPGA-UART-Transceiver

    UART communication link between two Altera Board (DE2-115)

    Language:Verilog

  • DatNT018/fpga-verilog-modules

    fpga modules

    Language:Verilog

  • mengstr/vuart

    WIP - Smallish UART written in Verilog

    Language:Verilog10

  • MohamedHussein27/UART-With-FIFOs

    This repository contains the Verilog implementation of a UART protocol with FIFOs for handling data transmission and reception.

    Language:Verilog10

  • TahirZia-1/UART

    A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

    Language:SystemVerilog10

  • TAlmeida003/uart-core

    UART Core com suporte a RTS/CTS para comunicação serial em FPGA. Projeto de Iniciação Científica (CNPq) do Telecore 64, um console portátil em FPGA que integra jogos 2D e controle de robôs, unindo sistemas embarcados, teleoperação e redes.

    Language:Verilog