zedboard
There are 78 repositories under zedboard topic.
bperez77/xilinx_axidma
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
MeowLucian/SDR_Matlab_OFDM_802.11a
:satellite: Using Software Designed Radio to transmit OFDM QPSK signals at 5 GHz
eliaskousk/parallella-riscv
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
WangXuan95/Zynq-Tutorial
使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例
MeowLucian/SDR_Matlab_OFDM_802.11n
:satellite: Using Software Designed Radio to transmit MIMO-OFDM QPSK signals at 5 GHz
Kenji-Ishimaru/polyphony
3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.
DLX4/zed_face
zedboard上基于FPGA+ARM的人脸识别智能监控系统。关键词：linux，zedboard，arm，fpga，人脸检测，人脸识别。
MeowLucian/SDR_FM_Radio
:radio: Using Software Designed Radio to transmit & receive FM signal
MeowLucian/SDR_Matlab_LTE
:satellite: Using Software Designed Radio to transmit LTE downlink signals at 2.4 GHz
MeowLucian/SDR_Matlab_OFDM_802.11a_16QAM
:satellite: Using Software Designed Radio to transmit OFDM 16QAM signals at 5 GHz
FloyedShen/mnist_hls
Lenet for MNIST handwritten digit recognition using Vivado hls tool
Goshik92/SHA256Hasher
SHA-256 IP core for ZedBoard (Zynq SoC)
delhatch/Zynq_UDP
Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.
sarthak268/Embedded_Logic_and_Design
This repository contains all labs done as a part of the Embedded Logic and Design course.
mmattioli/ZedBoard-OLED
Driving the OLED display on the ZedBoard
lvgl/lv_port_xilinx_zedboard_vitis
This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals
splAcharya/DigitalOscilloscope_Zynq7000Soc
A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.
delhatch/VGA_mem_mapped
Memory-mapped VGA display for Xilinx/Zynq/Zedboard, with demo code for using it.
bselimoglu/SoC-ZedBoard-Zynq-7000-Labs
Hardware and Software Co-design implementations
Fivefold/SRCNN
Super Resolution Convolutional Neural Network (SRCNN) for Python/Torch, Numpy and Avnet's ZedBoard
ugoleone/zedboard_image_processing_pipeline
FPGA based image processing pipeline using zedboard, able to accelerate openCV functions
HYSUM-TOBBETU/AES-Encryption-Verilog-Pipelined-Implementation-128bit
Device: Zedboard xc7z020clg484-1, Clock Rate: 319 MHz, Tool: Vivado 2018.3, Language: Verilog
delhatch/Zedboard_Mandel
Mandelbrot generator on the Zedboard. The image is output on the VGA port. Pure Verilog RTL, no ARM core.
eliaskousk/parallella-riscv-images
Parallella RISC-V Prebuilt Images
neeraj1397/Fast-Fourier-Transform-in-C
This repository contains the C code for ARM Implementation of FFT on Zynq-7000 APSoC from Xilinx.
zdzislaw-s/audio-processing
Simple audio processing with ADAU1761
zslwyuan/Zedboard_Intergrating_HLS_IP_AND_DDR
This is a project integrating HLS IP and CortexA9 on Zynq. This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART.
delhatch/IIR_EQ
IIR audio filter in Verilog, running on Zedboard. Fractional integer coefficients.
Goshik92/fsearch
FastSearch is a project intended to increase the speed of string searching by using the FPGA technology
Injabie3/dj-board
SFU - ENSC 452 (Advanced Digital System Design) Term Project: The Ultimate DJ Board using a Zedboard. Also mirrored on SFU CSIL's GitLab.
twosixlabs/ultrazed_dev
UltraZed Development
dougbrion/fpga-image-processing
Low latency FPGA based image processing (Zedboard)
Inception-framework/debugger
A low-latency USB3-based JTAG debugger.
mcagriaksoy/DegreeAdjustableRadar
Zynq ZedBoard SoC Lecture Final Project, degree adjustable ultrasonic sensor application
ArthyD/VHDLProjects
My VHDL academic projects including cryptography accelerators, a RISC-V processor implementation