zslwyuan/Zedboard_Intergrating_HLS_IP_AND_DDR
This is a project integrating HLS IP and CortexA9 on Zynq. This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART.
VHDL
No issues in this repository yet.
This is a project integrating HLS IP and CortexA9 on Zynq. This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART.
VHDL
No issues in this repository yet.