/VHDLProjects

My VHDL academic projects including cryptography accelerators, a RISC-V processor implementation

Primary LanguageVHDL

My VHDL Projects

These are my academic projects done with VHDL

E0 implementation

This project aims to implement the E0 crypto algorithm (for bluetooth communication). It is based on LFSR to generate pseudo random bit sequence.

Kogge-Stone adder

This project implements a trade-off design between ripple carry adders and carry lookahead adders for a 64 bits adder.

RISC-V implementation

This project provides a functionnal model and a RTL model implementing the RISC-V processor design.