Why RawModule instead of Module?
Closed this issue · 3 comments
When I compile riscv-boom with the latest hardfloat I have the following problem:
[error] (run-main-0) java.lang.reflect.InvocationTargetException
[error] java.lang.reflect.InvocationTargetException
[error] at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
[error] at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
[error] at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
[error] at java.lang.reflect.Constructor.newInstance(Constructor.java:423)
[error] at freechips.rocketchip.util.HasGeneratorUtilities.$anonfun$elaborate$1(GeneratorUtils.scala:55)
[error] at chisel3.Module$.do_apply(Module.scala:52)
[error] at chisel3.Driver$.$anonfun$elaborate$1(Driver.scala:93)
[error] at chisel3.internal.Builder$.$anonfun$build$2(Builder.scala:406)
[error] at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
[error] at chisel3.internal.Builder$.$anonfun$build$1(Builder.scala:404)
[error] at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
[error] at chisel3.internal.Builder$.build(Builder.scala:404)
[error] at chisel3.Driver$.elaborate(Driver.scala:93)
[error] hipyard at freechips.rocketchip.util.HasGeneratorUtilities.elaborate(GeneratorUtils.scala:60)
[error] Caused by: chisel3.internal.ChiselException: Error: No implicit clock.
[error] at chisel3.internal.throwException$.apply(Error.scala:85)
[error] at chisel3.internal.Builder$.$anonfun$forcedClock$1(Builder.scala:319)
[error] at scala.Option.getOrElse(Option.scala:189)
[error] at chisel3.internal.Builder$.forcedClock(Builder.scala:319)
[error] at chisel3.RegInit$.apply(Reg.scala:174)
[error] at chisel3.RegInit$.apply(Reg.scala:192)
[error] at Chisel.package$Reg$.apply(compatibility.scala:378)
[error] at hardfloat.DivSqrtRecF64ToRaw_mulAddZ31.(DivSqrtRecF64_mulAddZ31.scala:85)
[error] at hardfloat.DivSqrtRecF64_mulAddZ31.$anonfun$divSqrtRecF64ToRaw$1(DivSqrtRecF64_mulAddZ31.scala:750)
[error] at chisel3.Module$.do_apply(Module.scala:52)
[error] at hardfloat.DivSqrtRecF64_mulAddZ31.(DivSqrtRecF64_mulAddZ31.scala:750)
[error] at hardfloat.DivSqrtRecF64.$anonfun$ds$1(DivSqrtRecF64.scala:60)
[error] at chisel3.Module$.do_apply(Module.scala:52)
[error] at hardfloat.DivSqrtRecF64.(DivSqrtRecF64.scala:60)
[error] Nonzero exit code: 1
Please explain why the last correction is needed and give advice on how and where it is better to fix it.
It was necessary to support cleanly instantiating those modules inside modules whose implicit reset is asynchronous. cc @jerryz123
@aswaterman did you intend to make DivSqrtRecF4_mulAddZ31a RawModule? That module uses Reg internally, so it does not seem to be a unclocked module.