Comments on current version

[lonsing]

Hi Mario!

Thank you for your recent progress on this project!

I compiled some comments on the current version (commit 906274c)

instruction length parameter

• make the instruction length a parameter in the format file RV32M-ridecore_format.txt. The RISC-V specification in general allows instructions to be longer than 32 bits. The instruction length can then be treated as a parameter in the generator scripts.

file constraint_generator.py

• the generated constraints file misses the "allowed_*" assignment statements that are present in the code of the respective custom Verilog module.

• Similarly, also the FORMAT_I and FORMAT_R constraints are missing.

• We will eventually also need the assume property .

We wanted to avoid SystemVerilog as much as possible but we need to constrain the instructions to be only valid ones from the ISA. Yosys, which we are using with our model checker CoSA, can handle these constraints.

file modify_generator.py

• In the generated file modify_instruction.v the "instruction" is undefined. I think it should be possible to get rid of it and use qic_qimux_instruction instead.

• Wires like opcode, simm12, etc are declared as outputs but should be inputs.

file decoder_generator.py

• In the assignments of 'is_aluimm' etc. we make use of hardcoded 'opcode' constraints, which should ideally be avoided.

file qed_generator.py

• In the generated file qed.v, module 'qed_decoder' is instantiated but its input port 'ifu_qed_instruction' is not driven.

• files for modules qed_i_cache and qed_instruction_mux are currently not generated