The --fix_clusters option will result in conflicting locations during the placement stage.

[narutozxp]

If it has output pin constrains in the userplace.place file, Then, vpr will raise an error of conflicting locations.

Expected Behaviour

The pin location should be constrained by the userplace.place file without errors

Current Behaviour

Raising an error of conflicting locations

Possible Solution

Steps to Reproduce

constraints(userplace.place):

#Block Name	x	y	subblk
#----------	-	-	-
ina[0]	7	0	0
ina[1]	7	0	1
ina[2]	7	0	2
inb[0]	7	0	3
inb[1]	7	0	4
inb[2]	7	0	5
out:outc[0]	6	0	0
out:outc[1]	6	0	1
out:outc[2]	6	0	2
out:outc[3]	6	0	3

netlist((adder_bench.blif)

# Generated by Yosys 0.34+9 (git sha1 a79b15e94, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os)

.model adder_bench
.inputs clk rst_n ina[0] ina[1] ina[2] inb[0] inb[1] inb[2]
.outputs outc[0] outc[1] outc[2] outc[3]
.names $false
.names $true
1
.names $undef
.subckt adder a=ina_reg[0] b=inb_reg[0] cin=$add$./benchmark/adder_bench.v:70$3.genblk1.genblk1.genblk1.Cout_temp[0] cout=$add$./benchmark/adder_bench.v:70$3.genblk1.genblk1.genblk1.Cout_temp[1] sumout=$add$./benchmark/adder_bench.v:70$3.Y[0]
.subckt adder a=ina_reg[1] b=inb_reg[1] cin=$add$./benchmark/adder_bench.v:70$3.genblk1.genblk1.genblk1.Cout_temp[1] cout=$add$./benchmark/adder_bench.v:70$3.genblk1.genblk1.genblk1.Cout_temp[2] sumout=$add$./benchmark/adder_bench.v:70$3.Y[1]
.subckt adder a=ina_reg[2] b=inb_reg[2] cin=$add$./benchmark/adder_bench.v:70$3.genblk1.genblk1.genblk1.Cout_temp[2] cout=$add$./benchmark/adder_bench.v:70$3.genblk1.genblk1.genblk1.Cout_temp[3] sumout=$add$./benchmark/adder_bench.v:70$3.Y[2]
.subckt adder a=$false b=$false cout=$add$./benchmark/adder_bench.v:70$3.genblk1.genblk1.genblk1.Cout_temp[0]
.subckt adder a=$false b=$false cin=$add$./benchmark/adder_bench.v:70$3.genblk1.genblk1.genblk1.Cout_temp[3] sumout=$add$./benchmark/adder_bench.v:70$3.Y[3]
.subckt dffrn C=clk D=$add$./benchmark/adder_bench.v:70$3.Y[0] Q=outc[0] RN=rst_n
.subckt dffrn C=clk D=$add$./benchmark/adder_bench.v:70$3.Y[1] Q=outc[1] RN=rst_n
.subckt dffrn C=clk D=$add$./benchmark/adder_bench.v:70$3.Y[2] Q=outc[2] RN=rst_n
.subckt dffrn C=clk D=$add$./benchmark/adder_bench.v:70$3.Y[3] Q=outc[3] RN=rst_n
.subckt dffrn C=clk D=ina[0] Q=ina_reg[0] RN=rst_n
.subckt dffrn C=clk D=ina[1] Q=ina_reg[1] RN=rst_n
.subckt dffrn C=clk D=ina[2] Q=ina_reg[2] RN=rst_n
.subckt dffrn C=clk D=inb[0] Q=inb_reg[0] RN=rst_n
.subckt dffrn C=clk D=inb[1] Q=inb_reg[1] RN=rst_n
.subckt dffrn C=clk D=inb[2] Q=inb_reg[2] RN=rst_n
.end

commands

vpr k4n8_ahb_master_fifo_dpram.xml adder_bench.blif --device GW1N4_INTERFACE_WITHOUTDSP_64IO_12x12 --route_chan_width 100 --fix_clusters userplace.place --timing_tradeoff 1.0 --constant_net_method route --timing_report_detail detailed --sweep_dangling_blocks off

errot messages

## Initial Placement took 0.00 seconds (max_rss 61.9 MiB, delta_rss +0.0 MiB)
# Placement took 0.00 seconds (max_rss 61.9 MiB, delta_rss +0.0 MiB)
Error 1: 
Type: Placement
File: /home/data/shawn/eFPGA/Code/OpenFPGA/OpenFPGA_master/vtr-verilog-to-routing/vpr/src/base/read_place.cpp
Line: 255
Message: The location of cluster out:outc[0] (#4) is specified 2 times in the constraints file with conflicting locations. 
Its location was last specified with block out:outc[0]. 

Context

Your Environment

• VTR revision used: 8.1.0-dev
• Operating System and version: Ubuntu 22.04.4 LTS x86_64
• Compiler version: GNU 9.4.0 on Linux-5.15.0-46-generic x86_64