veryl-lang/veryl

Multiple clocks without clock domain annotation is allowed

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The following code is allowed now.
If there are multiple clocks in module, omitting annotation should be forbidden.

module ModuleA (
    i_clk_a: input clock,
    i_clk_b: input clock,
) {}

If both clocks belong the same clock domain, the following code is more clear.

// Both clock belong implicit clock domain
module ModuleA (
    i_clk_a: input '_ clock,
    i_clk_b: input '_ clock,
) {}

// Both clock belong domain 'a
module ModuleA (
    i_clk_a: input 'a clock,
    i_clk_b: input 'a clock,
) {}