veryl-lang/veryl

Assingment from generic instance is not identified

dalance opened this issue · 0 comments

o is unassigned warning occurs in the following code.

module ModuleA::<S> () {
    var o: logic;

    inst u: ModuleB::<S> (
        o  ,
    );
}

module ModuleB::<S> (
    o: output logic,
) {
    assign o = 0;
}