veryl-lang/veryl

Change symbol of clock domain annotation from `'` to `

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Now clock domain annotation uses ', but it is ambiguous between base-less number like 'hx.
This issue proposes using ` instead of ' for clock domain annotation.

Generally, ` is used as special string literal in Markdown, Javascript.
But I think ` can be used for this usage because HDL doesn't require many string literal types.

module ModuleA (
    i_clk_a: input `a clock,
    i_rst_a: input `a reset,
    i_clk_b: input `b clock,
    i_rst_b: input `b reset,
) {
}

Ref: #863