vinisha2410's Stars
ML4Comm-Netw/Paper-with-Code-of-Wireless-communication-Based-on-DL
无线与深度学习结合的论文代码整理/Paper-with-Code-of-Wireless-communication-Based-on-DL
omarelhedaby/CNN-FPGA
Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
VerificationExcellence/SystemVerilogReference
training labs and examples
VerificationExcellence/UVMReference
Reference examples and short projects using UVM Methodology
AniketBadhan/Convolutional-Neural-Network
Implementation of CNN using Verilog
Gowtham1729/Image-Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
LiXirong/AdaptiveFilterandActiveNoiseCancellation
Adaptive Filter and Active Noise Cancellation —— LMS, NLMS, RLS
padhi499/Image-Classification-using-CNN-on-FPGA
Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
FPGADude/Digital-Design
Verilog HDL files
WillGreen/timetoexplore
Source code to accompany https://timetoexplore.net
shariethernet/Physical-Design-with-OpenLANE-using-SKY130-PDK
This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified
maxs-well/LMS-sound-filtering-by-Verilog
LMS sound filtering by Verilog
RatkoFri/MulApprox
MulApprox - A comprehensive library of state-of-the-art approximate multipliers
mihir8181/VLSI-Design-Digital-System
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
FSq-Poplar/FPGA_NN
A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.
biren15/Design-and-implementation-of-the-low-pass-digital-filter
- Implemented 6th order low-pass digital filter for a speech signal sampled at 44KHz in Matlab FDA tool. - Created quantized RTL(second order filter instanciated thrice) in Verilog with the coefficients represented with 12 bits and maintained SNR of 36.89. - Analyzed the correlation of the Verilog implementation against the Matlab filter implementation by a self-checking script that compared the output of the Verilog implementation versus the Matlab output of the quantized filter and found the error to be 0%.
minhna1112/AdaptiveFilter-LMS-Verilog
Class Project - Digital Signal Processing
chkjacky/python-2s-complement-converter
A dec-bin converter uses 2's complement.
Aashish3970/MNIST_FPGA
3 layern artificial ANN to recognize handwritten digits and implement in FPGA
visnjicm/verilog-neural-network
Verilog implementation of a pre-trained handwritten digit recognition simple neural network.
KevinWang96/EE599_YihaoWang_7410178057
EE599 Accelerated Computing on FPGA
buttercutter/gilbert_cell_mixer
A gilbert cell mixer circuit implementation in LTSpice
guilherme-mendes/musical-bell-vhdl
Desenvolvimento de uma campainha musical que tocará uma música selecionada e programada na FPGA em VHDL.
PCov3r/FPGA_Handwritten_digit_recognition
A Verilog implementation of a hand-written digit recognition Neural Network
pparth27743/jpeg-image-compression
This project has 2 parts. (1) JPEG image compression is been implemented into Matlab and (2) Verilog language using Xilinx software.
bjones1/MSU-ECE-DSD
A course repository for ECE 4743/6743 – Digital Systems Design
klam20/FPGAProjects
Archfx/StopWatch-Basys3
Stopwatch ⏱️ implemented using Verilog with Vivado
nikhil1198/2-Stage-Operational-Amplifier
topalli16/Gilbert-Cell
Designed a Gilbert Cell in TSMC 0.18u process node. The Gilbert Cell is used for multiplication, modulation and phase detection.