vpetry

vpetry's Stars

• YosysHQ/yosys

  Yosys Open SYnthesis Suite

  Language:C++3.7k1371.8k918

• lnis-uofu/OpenFPGA

  An Open-source FPGA IP Generator

  Language:Verilog88143448169

• raysalemi/uvmprimer

  Contains the code examples from The UVM Primer Book sorted by chapters.

  Language:SystemVerilog514560211

• taichi-ishitani/tvip-axi

  AMBA AXI VIP

  Language:SystemVerilog3871541109

• cluelogic/uvm-tutorial-for-candy-lovers

  Source code repo for UVM Tutorial for Candy Lovers

  Language:SystemVerilog181182100

• olofk/corescore

  CoreScore

  Language:Verilog143101642

• vmmc2/Vulcan

  RISC-V Instruction Set Simulator (Built for education).

  Language:Dart1019010

• aignacio/riscv_verilator_model

  RISCV model for Verilator/FPGA targets

  Language:C495319

• Jeija/librenard

  Reverse Engineered Sigfox Stack - Library

  Language:C2310010

• aignacio/skid_buffer

  Language:Python420