vsdip
Open source developers partner with VSD and @kunalg123 for our approach to build content centric, research oriented flow to build a design and community.
VLSI System DesignOnline
Pinned Repositories
avsdbgp_3v3
avsdbdg_3v3 is a Bandgap Reference circuit, which is used to generate a constant voltage reference in analog domain which is independent of temperature and supply voltage variations.
avsddac_3v3
avsddac_3v3_sky130_v2
RISC-V-MYTH-Workshop
Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for Me in Thirty Hours" Workshop
rvmyth_avsddac_interface
VSD-IAT-Workshop-Github-Repos
GitHub is the new Resume for VLSI industry GitHub is indeed the new RESUME for VLSI industry. Really, if you are recruiting person and looking forward to judge a new candidate for a role in company, ask for GitHub project link. Projects written on resume and projects available on GitHub by a candidate will immediately give you an idea about his/her perseverance, dedication, sincerity, productivity and amount of hard-work he/she can put inside a project.
vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).
vsdsram
An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop) to store each bit. The size of SRAM specs is 32kbit/4k bytes with 1.8v. A 6T SRAM pairs up with two access transistors for read, write state and cross coupled inverter to hold/regenerate the state.
vsdsram_sky130
vsdStdCellCharacterizer_sky130
vsdip's Repositories
vsdip/vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).
vsdip/vsdsram
An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop) to store each bit. The size of SRAM specs is 32kbit/4k bytes with 1.8v. A 6T SRAM pairs up with two access transistors for read, write state and cross coupled inverter to hold/regenerate the state.
vsdip/avsdbgp_3v3
avsdbdg_3v3 is a Bandgap Reference circuit, which is used to generate a constant voltage reference in analog domain which is independent of temperature and supply voltage variations.