Pinned Repositories
AcceLeNetor
FYP project. A VerilogHDL based hardware accelerator.
Active-Client-Selection-for-Communication-efficient-Federated-Learning
Active Client Selection for Federated Learning
BearingPGA-Net
bert-on-silicon
Research and Materials on Hardware implementation of BERT (Bidirectional Encoder Representations from Transformers) Model
BlockConv
[TCAD 2021] Block Convolution: Towards Memory-Efficient Inference of Large-Scale CNNs on FPGA
BRAM_DDR3_HDMI
在FPGA中将图像数据输入到DDR3中,再输送到HDMI接口上进行显示。
Client_Selection_in_Federated_Learning_using_Matching-Based_Incentives
CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
CNN-hw-accelerator
CNN hardware accelerator to accelerate quantized LeNet-5 model
retraining-free-quantization
RFQuant: Retraining-free Model Quantization via One-Shot Weight-Coupling Learning, CVPR (2024)
vvvvain's Repositories
vvvvain/trans-fat
An FPGA Accelerator for Transformer Inference
vvvvain/Lenet-5_FPGA_Accelerator
vvvvain/CNNA
A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
vvvvain/FracBNN
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
vvvvain/EyerissF
An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"
vvvvain/MECOptimalOffloading
Optimization of Offloading Scheme Algorithm for Large Number of Tasks in Mobile-Edge Computing
vvvvain/CVPR2020_Auxiliary_Quantization
Training Quantized Neural Networks with a Full-precision Auxiliary Module
vvvvain/cnn_grinder
CNN-Grinder Workflow Project Files
vvvvain/Deep-Compression-PyTorch
PyTorch implementation of 'Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding' by Song Han, Huizi Mao, William J. Dally
vvvvain/FPGA_DPU
This project is to implement YOLO v3 on Xilinx FPGA with DPU
vvvvain/LeNet-CNN-Accelerator-Hardware-for-FPGA
An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
vvvvain/deep-learning-fpga
Source code for Final Year Thesis on implementations of deep learning accelerators on FPGAs.
vvvvain/zynqnet
Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"