Pinned Repositories
cocotbext-uart
UART cocotb module
cocotbext-wishbone
magenta
Magenta Microkernel
or1200mp
Multiprocessor variant of OpenRISC 1200 processor
riscv-ca-teaching
RISC-V in Practical Computer Architecture Education
riscv-cocotb
cocotb infrastructure for RISC-V core testing
riscv-python-model
Python Model of the RISC-V ISA
sungrow-websocket
Python Library to acees the websocket interface of Sungrow inverters
wavedrompy
WaveDrom compatible python command line
wb2axi
Wishbone to ARM AMBA 4 AXI
wallento's Repositories
wallento/or1200mp
Multiprocessor variant of OpenRISC 1200 processor
wallento/uart16550
Fork from OpenCores UART 16550
wallento/board_armjtag_pmod_compatible
Connector board (ARM) JTAG, Pmod compatible
wallento/mooreandmore
Data to print Moore's law
wallento/pmod_switchbox
Pmod Switchbox
wallento/component-libraries
EDA component libraries
wallento/lowrisc-fpga
Untethered (stand-alone) FPGA implementation of the lowRISC SoC
wallento/lowrisc-untether
lowRISC: Untethered Rocket on KC705 (and other FPGA boards)
wallento/mgpio
Multi-bank General Purpose I/O
wallento/newlib
Newlib mirror
wallento/nexys4ddr
Open source and properly licensed code for the Digilent Nexys 4 DDR peripherals
wallento/or1ksim_reentrant
Reentrant version of the OpenRISC simulator
wallento/orpsoc-cores
Core description files for ORPSoCv3
wallento/verilog-lib
Fine selection of small Verilog modules under MIT license
wallento/wb_interconnect
Wishbone Interconnect Modules
wallento/ArchC
Mirror of the ArchC Source Code
wallento/arm-trusted-firmware
ARM Trusted Firmware
wallento/glip
Generic Logic Interfacing Project
wallento/mad-workshop.de
MAD Workshop Website
wallento/openrisc-landing
Draft for OpenRISC landing page
wallento/optee_os
Trusted side of the TEE
wallento/or1k-ci-tests
OR1K Continuous Integration tests
wallento/or1k-gcc
wallento/or1k-src
OpenRISC 1000 port for sourceware.org's src tree (binutils, gdb, newlib, etc.)
wallento/or1ksim
The OpenRISC 1000 architectural simulator