/TakeRisc

A RISC-V RV32I Core written in TL-Verilog

TakeRisc

This repository contains the TL-Verilog design for a CPU Core implementing the RISC-V R32I ISA. If you want to build your own core, checkout this course.

TL-Verilog

TL-Verilog (Transaction-Level Verilog) is a HDL, which implements an abstraction layer on top of Verilog. To learn more, checkout their website.

How to run

  • Go to Makerchip
  • Create a new project
  • Copy/paste the content of core.tlv
  • Compile/Sim

Resources