Pinned Repositories
FPGA-USB-Device
An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
big-white-goose-e203
DC_fifo
drawio_mem
FPGA-USB-Device
FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.
SAR-ADC-FPGA
SparrowRV
An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
tt07-verilog-template
Submission template for Tiny Tapeout 7 - Verilog HDL Projects
USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
Yduck-processor
xiaowuzxc's Repositories
xiaowuzxc/SparrowRV
An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
xiaowuzxc/SAR-ADC-FPGA
xiaowuzxc/Yduck-processor
xiaowuzxc/big-white-goose-e203
xiaowuzxc/USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
xiaowuzxc/DC_fifo
xiaowuzxc/drawio_mem
xiaowuzxc/FPGA-USB-Device
FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.
xiaowuzxc/tt07-verilog-template
Submission template for Tiny Tapeout 7 - Verilog HDL Projects
xiaowuzxc/xiaowuzxc.github.io
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