ymherklotz/verismith
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
HaskellGPL-3.0
Issues
- 10
It would be nice to have a stack.yaml in the repo?
#103 opened by bojle - 0
- 1
- 6
- 0
- 1
can I use the EMI?
#95 opened by 1353369570 - 0
Update the nixpkgs pin to include vector 0.13
#96 opened by ymherklotz - 1
nix build failure on Ubuntu 20.04.6 LTS (GNU/Linux 5.15.90.1-microsoft-standard-WSL2 x86_64)
#98 opened by blackcoatzhou - 1
- 2
Add SystemVerilog parsers found in sv-tests?
#77 opened by mithro - 0
Shuffle signal and module instantiation
#81 opened by dwRchyngqxs - 0
- 0
verismith doesn't generate assign statements with concatenation and bit selectors in the LHS
#89 opened by yurivict - 0
The README section 'Build with cabal from source' should begin with 'cabal update'
#87 opened by yurivict - 19
I can't understand the readme you wrote
#79 opened by cemery123 - 1
"Resources" links are broken
#78 opened by forrestv - 0
Division with context-sensitive guards
#66 opened by ymherklotz - 0
Parallelise the reduction algorithm
#68 opened by ymherklotz - 0
Add python scripts into the main program
#56 opened by ymherklotz - 0
Add support for more Verilog constructs
#59 opened by ymherklotz - 0
- 0
Remove unsafe head from Lenses
#51 opened by ymherklotz - 3
License has contradictory wording
#72 opened by krupan - 0
Support combinational always blocks
#61 opened by ymherklotz - 1
run nix-build has no response
#71 opened by semiwizard - 3
cabal: Could not resolve dependencies:
#69 opened by semiwizard - 0
- 1
Add reduction algorithm optimisation
#60 opened by ymherklotz - 1
Add a rerun option instead of hijacking reduce
#57 opened by ymherklotz - 1
Error in for loop reduction
#64 opened by ymherklotz - 1
- 1
Fix parser with new modules
#65 opened by ymherklotz - 0
Update dependency for Hedgehog
#63 opened by ymherklotz - 0
Not all inputs get initialised in module
#54 opened by ymherklotz - 1
Fix resizing of module inputs and outputs
#52 opened by ymherklotz - 0
Implement some EMI approaches
#41 opened by ymherklotz - 1
Add Report type to generate reports from
#43 opened by ymherklotz - 1
Extend parser to accept all Verilog
#44 opened by ymherklotz - 0
Add documentation to all functions
#45 opened by ymherklotz - 0
Change the hierarchy of AST
#46 opened by ymherklotz - 1
Make findActiveWire work with SourceInfo
#50 opened by ymherklotz - 0
Add LDPE module to vivado cells
#49 opened by ymherklotz - 0
- 0
Add simulator options to config.toml
#48 opened by ymherklotz - 0
Think about removing the Arbitrary module
#47 opened by ymherklotz - 0
Add support for Covered
#42 opened by ymherklotz - 1
Remove quickcheck completely
#39 opened by ymherklotz - 0
- 0
Make types in AST more efficient
#36 opened by ymherklotz - 0
Parser not identifying input and output
#38 opened by ymherklotz