ymherklotz/verismith
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
HaskellGPL-3.0
Stargazers
- alaksana96@signal-ai
- AlexMontgomerieImperial College London
- ben-marshall
- buttercutter
- cbalint13Earth, MilkyWay, Laniakea
- daveshah1
- divyanshmanochaImperial College London
- eddiehung@FPGeh / University of British Columbia
- hailinzengBeijing, China
- hsed
- ironsteelPlovdiv/Bulgaria
- jevinskieLafayette, Indiana
- jianyichengUniversity of Cambridge
- johnwickersonImperial College London
- JSP110
- lethalbit@YosysHQ
- luinaudtPolytechnique Montréal
- ly0Shenzhen, PRC
- maccthLondon
- martinferiancUniversity College London
- MattPD
- medson10Votorantim, Brazil
- MerelyLogicalCambridge
- mithro@timvideos
- ps-george
- renauUCSC
- rroohhh
- shapr@RecurseCenter
- SiegfriedchaoCenter for Molecular Materals, Photonics and Electronics, Department of Engineering, Unviersity of Cambridge
- smorimoto@ocaml @tc39
- STFlemingResearcher
- suotoUnited Kingdom
- ThunderMikeyCambridge
- tomoveu
- ufwt
- whitequark@ChipFlow