Width extension converts string to int and changes endianess / byte order

[vogelpi]

Hi @zachjs ,
I just noticed an issue that seems to have been introduced somewhere between version 0.0.9-24 and current 0.0.11 (I know there has been quite some time and work in between, sorry). Namely, it seems that newer versions convert a width extended string e.g. 64'("GA") into an integer 64'("16711") (== 64'h4147) where previous versions would just leave 64'("GA").

This can be an issue when later during synthesis (e.g. using Yosys) a string parameter is compared against this integer. Because the string "GA" in synthesis is converted to 16'01000111_01000001 (== 16'h4741), i.e., the bytes are in the opposite order. The string won't match.

I give you a minimal code snippet:

module example #(
  parameter Type = "GA"
) (
  input in_i,
  output out_o
);

  if (64'(Type) == 64'("GA")) begin : gen_ga
    assign out_o = in_i;
  end else begin : gen_not_ga
    assign out_o = ~in_i;
  end

endmodule

With sv2v-0.0.9-24:

module example (
	in_i,
	out_o
);
	parameter Type = "GA";
	input in_i;
	output wire out_o;
	function automatic [63:0] sv2v_cast_64;
		input reg [63:0] inp;
		sv2v_cast_64 = inp;
	endfunction
	generate
		if (sv2v_cast_64(Type) == sv2v_cast_64("GA")) begin : gen_ga
			assign out_o = in_i;
		end
		else begin : gen_not_ga
			assign out_o = ~in_i;
		end
	endgenerate
endmodule

and with sv2v-0.0.11:

module example (
	in_i,
	out_o
);
	parameter Type = "GA";
	input in_i;
	output wire out_o;
	function automatic [63:0] sv2v_cast_64;
		input reg [63:0] inp;
		sv2v_cast_64 = inp;
	endfunction
	generate
		if (sv2v_cast_64(Type) == 64'd16711) begin : gen_ga
			assign out_o = in_i;
		end
		else begin : gen_not_ga
			assign out_o = ~in_i;
		end
	endgenerate
endmodule

[zachjs]

Thank you for filing this issue! Indeed sv2v was using the wrong byte order. This should be fixed as of 81d8225. Can you try it out?

[vogelpi]

Fantastic! Many thanks @zachjs for the quick fix! I've tested the latest version and it works as expected.