Missing "wire" keyword

[ldoolitt]

With this 94-line test case
test3.txt (cut back from 2464 lines of production code) a couple of signals get declared as "signed" instead of "wire signed". That makes the sv2v output at least incompatible with iverilog.

$ sv2v test3.sv > foo.v
$ iverilog -Wall foo.v
foo.v:77: syntax error
foo.v:77: error: invalid module item.
foo.v:78: syntax error
foo.v:78: error: invalid module item.
$ sed -e 's/      signed /        wire signed /' < foo.v > foo_fixed.v # the first character of the regex should be a tab 
$ iverilog -Wall foo_fixed.v 
$

I suspect this test case can be cut back even more. I'll leave that job to someone who understands SystemVerilog better than me.

[zachjs]

Thank you for filing an issue with such a nice reduced test case! This should be fixed in 1b27343. Please let me know if It works for you!

[ldoolitt]

Yes, it works now. Thanks!