zhangburch

zhangburch's Stars

• liangzhy2/CK_Riscv

  Try BE flow & study icc2 script

  Language:Tcl31

• Digital-EDA/Digital-IDE

  All in one vscode plugin for HDL development

  Language:Verilog36710

• adki/gen_amba_2021

  AMBA bus generator including AXI4, AXI3, AHB, and APB

  Language:C16842

• taoyilee/clacc

  Deep Learning Accelerator (Convolution Neural Networks)

  Language:Verilog16058

• antonson-j1/SHA256-Accelerator-Hardware

  This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accelerator with gradual improvements through spatial pre-computation techniques and pipelining. The SHA256 accelerators are implemented using Verilog and synthesized using Yosys Open Synthesis Suite. The optimized designs are then compared with a base-line C implementation in software. Hash functions are used to securely store passwords, to quickly store and retrive data, and also to check if a file/message is corrupted.

  Language:Verilog192

• starkerfirst/USTC_2022FA_ICdesign

  Design a micro chip in TSMC .18um process, including a mips cpu (8 bit) and a systolic array accelerator

  Language:Verilog51

• spokeyjoe/LoongArchCPU

  A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.

  Language:Verilog131

• saikat27/riscvofdm

  An OFDM Accelerator for RISC-V based Processors

  Language:Verilog83

• RomanRevzin/riscv_ai_accelerator

  This is a small Verilog project for Hackaton at Ruppin Academic College. Given a RISCV processor, we've been asked to extends it's abilities by adding number of modules.

  Language:Verilog3

• XhyDds/creep

  Language:Verilog71

• LainChip/LainSoC

  System-on-Chip designed for Lain Core on NSCSCC board

  Language:Verilog3

• psuggate/axi-ddr3-lite

  AXI DDR3 SDRAM Memory Controller for Xilinx GoWin Altera Intel Lattice FPGAs, written in Verilog.

  Language:Verilog2

• PaserTech-Hardware/GowinDDR3_AXI4_SpinalHDL

  Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现

  Language:Verilog186

• HiggsBose/RiscV_CPU_with_Accelerator

  A RiscV CPU with an accelerator for accelerating neural networks attached to it

  Language:Verilog32

• XueTianyu24/cnn_accelerator

  【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器

  Language:Verilog12326

• gpakosz/.tmux

  🇫🇷 Oh my tmux! My self-contained, pretty & versatile tmux configuration made with ❤️

  Language:Shell21.8k3.4k

• tastynoob/aura-core

  "aura" my super-scalar O3 cpu core

  Language:SystemVerilog24

• lty2002/my-code-for-android

  Language:Kotlin6

• ljlin/MIPS48PipelineCPU

  5 stage pipelined MIPS-32 processor

  Language:Verilog5511

• tom01h/zero-riscy

  zero-riscy CPU Core

  Language:SystemVerilog134

• tilk/riscv-simple-sv

  A simple RISC V core for teaching

  Language:SystemVerilog16519

• eugene-tarassov/vivado-risc-v

  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

  Language:Tcl820186

• sifive/riscv-cores-list

  RISC-V Cores, SoC platforms and SoCs

  42

• vinceliuice/WhiteSur-gtk-theme

  MacOS Big Sur like theme for Gnome desktops

  Language:SCSS5.8k600

• mfkiwl/E203_dma

  8

• sergeykhbr/riscv_vhdl

  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

  Language:Verilog619102

• SI-RISCV/e200_opensource

  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

  Language:Verilog2.6k1k

• xiaoerlang0359/E203plus

  upgrade to e203 (a risc-v core)

  Language:Verilog3613

• Wsine/feishu2md

  一键命令下载飞书文档为 Markdown

  Language:Go1.1k109

• liangkangnan/tinyriscv

  A very simple and easy to understand RISC-V core.

  Language:C1.1k184