zhanghaim's Stars
VerificationExcellence/SystemVerilogReference
training labs and examples
efabless/caravel
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
efabless/raven-picorv32
Silicon-validated SoC implementation of the PicoSoc/PicoRV32
Practical-UVM-Step-By-Step/Practical-UVM-Step-By-Step
This is the main repository for all the examples for the book Practical UVM
efabless/caravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
mayurkubavat/UVM-Examples
UVM examples and projects
Verdvana/AXI4_Interconnect
AXI总线连接器
VerificationExcellence/SystemVerilogAssertions
Examples and reference for System Verilog Assertions
sach/System-Verilog-Packet-Library
System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
muneebullashariff/axi4_vip
Verification IP for APB protocol
wangjidwb123/AHB-SRAMC
IC Verification & SV Demo
Shehab-Naga/ddr5_phy
DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
JoseIuri/UVM-APB_RAL
This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
Aperture-Electronic/SystemVerilog-Bitmap-Library-AXI-Image-VIP
Bitmap Processing Library & AXI-Stream Video Image VIP
zhajio1988/ExtremeDV_UVM
UVM resource from github, run simulation use YASAsim flow
programer-guan/digital_ic_verification
数字IC验证案例（SV and UVM）
mayurkubavat/SystemVerilog
SystemVerilog examples and projects
pendkeomkar/SPI
Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.
Harshil1995/I2C_UVM_APB
Formulated testbench using System Verilog and UVM and verified I2C bus controller with APB interface
biukang/Spider
Linux平台，基于C语言的简易爬虫
Raghavi9860/UVM_based_Verification_of_APB_protocol
APB Protocol is designed and verified using System Verilog based UVM. The tool used in designing and simulation is EDA Playground.
RyanHunter-DV/vips
for IC verification IP
zhangershuo/system_verilog-labs
Digital IC Verification, using system Verilog to verify the functions of preprocessing module and ALU
2019-MSEE-40/Verification-of-AHB-Lite-Memory
Project for course EE-599B: SoC Verification in System- Verilog
markos-stefanidis/riscv-rv32im-core
System Verilog Implementation of a basic Risc-V core.
alishairkhan7385/RISC-V-Single-Cycle-Datapath-in-System-verilog
rv32i implementing all base instructions.
OmarAbdelSamea/system-verilog-scoreboard
Simple system verilog program with a testbench example