/neorv32-setups

:file_folder: Exemplary NEORV32 setups for various FPGA boards and toolchains.

Primary LanguageVHDLBSD 3-Clause "New" or "Revised" LicenseBSD-3-Clause

neorv32-setups: Exemplary FPGA Board Setups

Containers Implementation Gitter

This repository provides exemplary NEORV32 SoC setups and projects for different FPGA platforms/boards and various toolchains. You can directly use one of the provided setups or use them as starting point to build your own setup. Project maintainers may make pull requests against this repository to add or link their setups.

💡 Ready-to-use bitstreams for the provided open source toolchain-based setups are available via the assets of the Implementation Workflow.

Setups using Commercial Toolchains

The setups using commercial toolchains provide pre-configured project files that can be opened with the according FPGA tools.

Setup Toolchain Board FPGA Author(s)
📁 de0-nano-test-setup Intel Quartus Prime Terasic DE0-Nano Intel Cyclone IV EP4CE22F17C6N stnolting
📁 de0-nano-test-setup-qsys Intel Quartus Prime Terasic DE0-Nano Intel Cyclone IV EP4CE22F17C6N torerams
📁 de0-nano-test-setup-avalonmm Intel Quartus Prime Terasic DE0-Nano Intel Cyclone IV EP4CE22F17C6N torerams
📁 terasic-cyclone-V-gx-starter-kit-test-setup Intel Quartus Prime Terasic Cyclone-V GX Starter Kit Intel Cyclone V 5CGXFC5C6F27C7N zs6mue
📁 UPduino_v3 Lattice Radiant tinyVision.ai Inc. UPduino v3.0 Lattice iCE40 UltraPlus iCE40UP5K-SG48I stnolting
📁 arty-a7-35-test-setup Xilinx Vivado Digilent Arty A7-35 Xilinx Artix-7 XC7A35TICSG324-1L stnolting
📁 nexys-a7-test-setup Xilinx Vivado Digilent Nexys A7 Xilinx Artix-7 XC7A50TCSG324-1 AWenzel83
📁 nexys-a7-test-setup Xilinx Vivado Digilent Nexys 4 DDR Xilinx Artix-7 XC7A100TCSG324-1 AWenzel83
🌍 custom CRC32 processor module for the nexys-a7 boards (tutorial) Xilinx Vivado Digilent Nexys A7 Xilinx Artix-7 XC7A50TCSG324-1 motius (ikstvn, turbinenreiter)
🌍 neorv32-examples Intel Quartus Prime Different Terasic boards Different Intel FPGAs emb4fun

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Setups using Open-Source Toolchains

All setups using open-source toolchains are located in the osflow folder. See the README there for more information how to run a specific setup and how to add new targets.

Setup Toolchain Board FPGA Author(s)
📁 UPDuino-v3.0 GHDL, Yosys, nextPNR UPduino v3.0 Lattice iCE40 UltraPlus iCE40UP5K-SG48I tmeissner
📁 FOMU GHDL, Yosys, nextPNR FOMU Lattice iCE40 UltraPlus iCE40UP5K-SG48I umarcor
📁 iCESugar GHDL, Yosys, nextPNR iCESugar Lattice iCE40 UltraPlus iCE40UP5K-SG48I umarcor
📁 AlhambraII GHDL, Yosys, nextPNR AlhambraII Lattice iCE40HX4K zipotron
📁 Orange Crab GHDL, Yosys, nextPNR Orange Crab Lattice ECP5-25F umarcor, jeremyherbert
📁 ULX3S GHDL, Yosys, nextPNR ULX3S Lattice ECP5 LFE5U-85F-6BG381C zipotron
📁 ChipWhisperer iCE40CW312 GHDL, Yosys, nextPNR CW312T_ICE40UP Lattice iCE40 UltraPlus iCE40UP5K-UWG30 colinoflynn
🌍 ULX3S-SDRAM GHDL, Yosys, nextPNR ULX3S Lattice ECP5 LFE5U-85F-6BG381C zipotron

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Adding Your Project Setup

Please respect the following guidelines if you'd like to add or link your setup to the list:

  • check out the project's code of conduct
  • add a link if the board you are using provides online documentation or can be purchased somewhere
  • use the 📁 emoji (:file_folder:) if the setup is located in this repository; use the 🌍 emoji (:earth_africa:) if it is a link to your local project
  • please add a README.md file to give some brief information about the setup and a .gitignore file to keep things clean
  • if you like you can add your setup to the implementation GitHub actions workflow to automatically generate up-to-date bitstreams for your setup

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Setup-Specific NEORV32 Software Framework Modifications

In order to use the features provided by the setups, minor optional changes can be made to the default NEORV32 setup.

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