1Jerry2Zhao3's Stars
Tencent/TNN
TNN: developed by Tencent Youtu Lab and Guangying Lab, a uniform deep learning inference framework for mobile、desktop and server. TNN is distinguished by several outstanding features, including its cross-platform capability, high performance, model compression and code pruning. Based on ncnn and Rapidnet, TNN further strengthens the support and performance optimization for mobile devices, and also draws on the advantages of good extensibility and high performance from existed open source efforts. TNN has been deployed in multiple Apps from Tencent, such as Mobile QQ, Weishi, Pitu, etc. Contributions are welcome to work in collaborative with us and make TNN a better framework.
openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
tensil-ai/tensil
Open source machine learning accelerators
abs-tudelft/fletcher
Fletcher: A framework to integrate FPGA accelerators with Apache Arrow
avanetten/yoltv5
YOLT, now with PyTorch.
19801201/SpinalHDL_CNN_Accelerator
CNN accelerator implemented with Spinal HDL
Chainsaw-Team/Chainsaw
a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications
SFU-HiAccel/SyncNN
[FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.
cvdong/YOLO_TRT_SIM
高效部署:YOLO X, V3, V4, V5, V6, V7, V8, EdgeYOLO TRT推理 ™️ :top: ,前后处理均由CUDA核函数实现 CPP/CUDA🚀
Shehab-Naga/ddr5_phy
DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
PacoReinaCampo/SoC-DV
System on Chip verified with UVM/OSVVM/FV
jackhanyuan/yolov5-ascend
YOLOv5 om model inference program on the Huawei Ascend platform
kkenshin1/AXI-Ethernet-UVM
A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
rits-drsl/ZybotR2-96-fpt19
An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019
openhwgroup/core-v-mcu-uvm
CORE-V MCU UVM Environment and Test Bench
SFU-HiAccel/CHIP-KNN
[TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs
muneebullashariff/pulpino_soc_uvm_testbench
UVM testbench for verifying the Pulpino SoC
XBQ314/A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-Units
Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现,基为2,有两个并行的蝶形单元
Nikola2444/RISC-V-vector-processor
parallel-ml/Capella-FPL19-SplitNetworksOnFPGA
FPL'19 Demo - Splitted Network on Collaborative PYNQ FPGAs
shin-yamashita/5th-AI-Edge-Contest
RTL implementation of TFlite FPGA accelerator and RISC-V controller.
Tai-Min/KV260-Human-Detector
3D Lidar based neural human detector on Kria KV260. Part of Adaptive Computing Challenge 2021 with AMD-Xilinx
ccys-a11y/dac_sdc_2022
This project is about a FPGA-based neural network inference accelerator, which is designed with HLS tool.
arpangoswami/image_enhance_combiner_python
Combines a high resolution grayscale image with a low resolution panchromatic image first using wavelet fusion, then passes it through a Gaussian filter for sharpening and then passes it through a theano neural network
HyeongjuKang/accelerator-aware-pruning
liushuan/MLU270-220
寒武纪模型转换流程代码
miltosmac/SODA
Accelerated Stencil Computation with Optimized Dataflow Architecture on FPGAs
yphone/FCCM2021-GVPF-E
eroor8/fccm2022demo_concept_drift
Demo of online training with concept drift for FCCM 2022 demo night
HyeongjuKang/aocstream