1sand0s/SSP-Master-and-Slave-Verilog-Module

FSM based SPI/SSP Master and Slave Verilog Module

SSP-Master-and-Slave-Verilog-Module

FSM based SSP Master and Slave Verilog Module

For more details please refer to https://1sand0s.github.io/designing-spi-master-and-slave-in-verilog-synthesizable.html