Pinned Repositories
ApogeoRV
A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
Arithmetic-Circuits
This repository contains different modules which execute arithmetic operations.
FIFO
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
GabbedT
Informations
ISW_AA22-23
Main repository of the group project for the class: Software Engineering. Project members: Gabriele Tripi, Andrea Raineri, Salvatore Lo Piccolo
riscv-isa-manual
RISC-V Instruction Set Manual
UART-Controller
UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the device synthesis and simulation, as well as a simple driver to use it in your system.
ZenithSoC
General purpose FPGA based System On Chip built around a powerful RISC-V 32 bit CPU.
riscv-isa-manual
RISC-V Instruction Set Manual
GabbedT's Repositories
GabbedT/ApogeoRV
A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
GabbedT/FIFO
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
GabbedT/UART-Controller
UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the device synthesis and simulation, as well as a simple driver to use it in your system.
GabbedT/Arithmetic-Circuits
This repository contains different modules which execute arithmetic operations.
GabbedT/ZenithSoC
General purpose FPGA based System On Chip built around a powerful RISC-V 32 bit CPU.
GabbedT/GabbedT
Informations
GabbedT/ISW_AA22-23
Main repository of the group project for the class: Software Engineering. Project members: Gabriele Tripi, Andrea Raineri, Salvatore Lo Piccolo
GabbedT/riscv-isa-manual
RISC-V Instruction Set Manual