GabbedT

GabbedT's Stars

• cfenollosa/os-tutorial

  How to create an OS from scratch

  Language:C27.3k7981763.3k

• ggambetta/computer-graphics-from-scratch

  Text, diagrams, and source code for the book Computer Graphics from scratch.

  1.2k4517117

• itsfrank/MinecraftHDL

  A Verilog synthesis flow for Minecraft redstone circuits

  Language:SystemVerilog1.1k171125

• KLayout/klayout

  KLayout Main Sources

  Language:C++804441.1k205

• The-OpenROAD-Project/OpenSTA

  OpenSTA engine

  Language:C++40930171173

• HewlettPackard/cacti

  An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model

  Language:C++4072017139

• The-OpenROAD-Project/OpenROAD-flow-scripts

  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

  Language:Verilog33912388290

• StefanSchippers/xschem

  A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

  Language:C3331723521

• RTimothyEdwards/open_pdks

  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

  Language:Python2922021786

• SpinalHDL/NaxRiscv

  Language:Scala2692511240

• ucb-bar/hammer

  Hammer: Highly Agile Masks Made Effortlessly from RTL

  Language:Python2553336759

• mflowgen/mflowgen

  mflowgen -- A Modular ASIC/FPGA Flow Generator

  Language:Python232183352

• RTimothyEdwards/qflow

  Qflow full end-to-end digital synthesis flow for ASIC designs

  Language:C193154737

• mflowgen/freepdk-45nm

  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

  Language:Verilog1508433

• akilm/Physical-Design

  Physical Design Flow from RTL to GDS using Opensource tools.

  834015

• andres-mancera/ethernet_10ge_mac_SV_tb

  SystemVerilog testbench for an Ethernet 10GE MAC core

  Language:Verilog444017

• wavedrom/vcd-samples

  sample VCD files

  36412

• XarkLabs/Xosera

  Xark's Open Source Embedded Retro Adapter - FPGA based video for rosco_m68k and others

  Language:C36839

• chipsalliance/UHDM-integration-tests

  Language:Verilog30142228

• GabbedT/ApogeoRV

  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

  Language:SystemVerilog16101

• aasthadave9/Advanced-Physical-Design-Using-OpenLANE-Sky130

  This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130

  14205

• GabbedT/FIFO

  FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.

  Language:SystemVerilog4100

• GabbedT/UART-Controller

  UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the device synthesis and simulation, as well as a simple driver to use it in your system.

  Language:SystemVerilog4100

• robotman2412/nebula-risc-v

  A collaborative RISC-V CPU project

  Language:Scala4260

• GabbedT/Arithmetic-Circuits

  This repository contains different modules which execute arithmetic operations.

  Language:SystemVerilog3100

• sidlathar/assertions-project-slathar

  Language:SystemVerilog1

• sidlathar/memorycontroller-slathar

  Language:SystemVerilog1

• sidlathar/router-slathar

  Language:SystemVerilog1

• sidlathar/usb-controller

  Language:SystemVerilog1

• vincenzogiannone/OpenRAM_Sky130PDK_multiport

  Adapted code to generate multiported SRAMs in Skywater 130 PDK

  Language:Python1101