/100-DAYS-OF-RTL

This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools

Primary LanguageVerilog

100-DAYS-OF-RTL

HELLO VLSI ENTHUSIASTS, WELCOME TO MY 100DAYSOFRTL REPO

My Name is Jayaram G, I mostly use Xilinx ISE 14.7 Design Suite for the simulation of RTL Codes.

Here is the list of Day wise RTL Codes:

Day-1 : HALF ADDER (Three Modelling styles).

Day-2 : FULL ADDER (Three Modelling styles).

Day-3 : HALF SUBTRACTOR (Three Modelling styles).

Day-4 : FULL SUBTRACTOR (Three Modelling styles).

Day-5 : MUX 8:1 (Three Modelling styles).

Day-6 : DEMUX 1:8 (Three Modelling styles).

Day-7 : ENCODER 8:3 (Three Modelling styles).

Day-8 : DECODER 3:8 (Three Modelling styles).

Day-9 : CLOCK DIVIDER BY 2 POWERS (Behavioral Modelling).

Day-10 : CLOCK DIVIDER BY 3 (Behavioral Modelling).

Day-11 : RIPPLE CARRY ADDER (Structural Modelling).

Day-12 : 8-BIT ALU [ARITHMETIC & LOGICAL UNIT] (Behavioral Modelling).

DAY-13 : BCD TO 7-SEGMENT DISPLAY (Behavioral Modelling).

DAY-14 : BINARY TO GRAY CONVERTER (Three Modelling styles).

DAY-15 : GRAY TO BINARY CONVERTER (Three Modelling styles).

DAY-16 : 4-BIT MAGNITUDE COMPARATOR (Behavioral Modelling).

DAY-17 : 3-BIT EVEN & ODD PARITY GENERATOR (Dataflow Modelling).

DAY-18 : 3-BIT EVEN & ODD PARITY CHECKERS (Dataflow Modelling).

DAY-19 : 8:3 PRIORITY ENCODER (Behavioral Modelling).

DAY-20 : FLIPFLOPS (Behavioral Modelling).

DAY-21 : SISO [SERIAL-INPUT SERIAL-OUTPUT] SHIFT REGISTERS (Behavioral & Structural Modelling).

DAY-22 : SIPO [SERIAL-INPUT PARALLEL-OUTPUT] SHIFT REGISTERS (Behavioral & Structural Modelling).

DAY-23 : PIPO [PARALLEL-INPUT PARALLEL-OUTPUT] SHIFT REGISTERS (Behavioral & Structural Modelling).

DAY-24 : PISO [PARALLEL-INPUT SERIAL-OUTPUT] SHIFT REGISTERS (Structural Modelling).

DAY-25 : BI-DIRECTIONAL SHIFT REGISTER (Behavioral Modelling).

DAY-26 : UNIVERSAL SHIFT REGISTER (Behavioural Modelling).

DAY-27 : 4-BIT ASYNCHROUNOUS(RIPPLE) UP COUNTER (Structural Modelling).

DAY-28 : 4-BIT ASYNCHROUNOUS(RIPPLE) UP-DOWN COUNTER (Structural Modelling).

DAY-29 : 3-BIT SYNCHROUNOUS UP COUNTER (Structural Modelling).

DAY-30 : 3-BIT SYNCHROUNOUS UP-DOWN COUNTER (Structural Modelling).

DAY-31 : RING COUNTER (Behavioral Modelling) & JOHNSON COUNTER (Behavioral Modelling).

DAY-32 : 1010 SEQUENCE DETECTOR USING MOORE FSM [OVERLAPPING & NON-OVERLAPPING TECHNIQUES] (Behavioral Modelling).

DAY-33 : 1010 SEQUENCE DETECTOR USING MEALY FSM [OVERLAPPING & NON-OVERLAPPING TECHNIQUES] (Behavioral Modelling).

FSM-BASED-VERILOG-MINI-PROJECTS

DAY-34 : VERILOG MINI PROJECT_1 : DESIGNING A VENDING MACHINE WITH CHANGE MECHANISM

DAY-35 : VERILOG MINI PROJECT_2 : DESIGNING AN AUTOMATIC WASHING MACHINE

DAY-36 : VERILOG MINI PROJECT_3 : DESIGNING A TRAFFIC LIGHT CONTROLLER SYSTEM FOR T-INTERSECTION

DAY-37 : VERILOG MINI PROJECT_4 : DESIGNING A CAR PARKING SYSTEM WITH PARKING SPACE MANAGEMENT

DAY-38 : SINGLE PORT AND DUAL PORT RAM & ROM (Behavioral Modelling).

DAY-39 : 8-BIT VEDIC MULTIPLIER (Structural Modelling).

DAY-40 : 8-BIT BARREL SHIFTER (Behavioral Modelling).

DAY-41 : PWM SIGNAL GENERATOR.

DAY-42 : POSEDGE & NEGEDGE DETECTOR.

DAY-43 : GCD CALCULATOR FOR 2 N-BIT NUMBERS (Behavioral Modelling).

FPGA-BASED-IMPLEMENTATIONS

DAY-44 : IMPLEMENTATION OF BCD TO 7-SEGMENT DISPLAY ON FPGA.

DAY-45 : IMPLEMENTATION OF BLINGKING OF LED.

DAY-46 : PWM GENERATOR FOR LED BIGHTNESS MANAGEMENT.

DAY-47 : DEBOUNCING OF BUTTONS USING FSM.