xilinx-ise
There are 99 repositories under xilinx-ise topic.
duskwuff/Xilinx-ISE-Makefile
An example of how to use the Xilinx ISE toolchain from the command line
pontazaricardo/Verilog_Calculator_Matrix_Multiplication
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
mcagriaksoy/VHDL-FPGA-LAB_PROJECTS
My Lab Assigments from Bachelor Degree, This repo includes the projects for digital systems II Lecture (EEM334)
JAYRAM711/100-DAYS-OF-RTL
This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools
ViktorSlavkovic/FPGA_Tetris
FPGA Tetris written in Verilog
mesarcik/MANDELBROT
A Verilog based Fractal Set Generator for the Xilinx Artix 7
islandcontroller/ArduinoXVC
Xilinx Virtual Cable (XVC) Server implementation for use with an Arduino UNO/Leonardo
maazm007/100Daysof_RTL
The Repository contains the code of various Digital Circuits
tarlaun/CORDIC
Digital System Design Project - Spring 2020
zpekic/tinycomputer
Tiny 4-bit CPU using AMD2901 bit slice (https://github.com/Amrnasr/AM2901) and program memory initialized from a file
Saadia-Hassan/8x8Multiplier-Using-Vedic-Mathematics
An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.
zpekic/sys9080
Simple system built around VHDL implementation of Am9080 8-bit CPU based on 29XX bit-slice series of devices, as described here: https://en.wikichip.org/w/images/7/76/An_Emulation_of_the_Am9080A.pdf
SamuelGong/SingleCycleCPU
A single cycle CPU running MIPS instructions on Xilinx FPGA
Hamid-R-Tanhaei/AX309-RTC-UART-VHDL
ALINX-AX309-RTC-UART-VHDL-FPGA-Xilinx-Spartan6
MaharshSuryawala/Microprocessor-Without-Interlocked-Pipeline-Stages-MIPS
RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.
PrayagS/MIPS_16bit
16-bit MIPS processor implemented in Verilog (as a part of Computer Organisation course)
rv2442/16BitScientificCalculator
16 Bit Scientific Calculator Using Xilinx ISE 14.7 on Xilinx ISE, EDA Playground and Simple 4 bit calculator on Spartan 6 Board
vinayak1998/Reflex-Tester
This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.
ashvnv/FPGA-Ping-Pong-game
Simple Ping Pong game on Xilinx Spartan 3E
ctsiaousis/mipsMultiCycleProcessor
A VHDL implementation of a MIPS processor with multicycle instruction fetching
hpaluch/crnr-ii-intro
Introductory Verilog project for Digilent CoolRunner-II Starter Board featuring Xilinx XC2C256-7-TQ144 CPLD
MossbauerLab/MessbauerTestEnvironment
FPGA Messbauer hardware (generator, emulation of signal from gamma-source registered and amplified
SamuelGong/MultipleCycleCPU
A multiple cycle CPU running MIPS instructions on Xilinx FPGA
unipieslab/sevax
Soft Error Vulnerability Analysis Framework for Xilinx FPGAs
vinayak1998/7-segment-display-fpga
Design and implement a Seven Segment Display available on the BASYS3 board (FPGA) in VHDL
zpekic/sys_primegen
Signed / unsigned multiplier / divider used by a microcode-driven prime number generator
andrsmllr/spartan3e_starter_devbrd
Play and learn with the Digilent Spartan3E-Starter board featuring a Xilinx Spartan-3E XC3S500E FPGA and various peripherals.
aydnzn/Digital-System-Design
A repository for Digital System Design Laboratory, providing labs and a project covering digital circuits, CAD tools, VHDL, FPGA, and ICs.
ismenc/fpga-vga-driver-game
This is 'space invaders' game and VGA driver builded on Xilinx ISE + Spartan 3
kaushanr/System-Bus-Design
Design of a system bus architecture - Team Project @ ENTC UoM
maazm007/4_Bit_Signed_Calculator
Hardware Schematic of Four Bit Signed Calculator designed using Xilinx ISE 14.7
maazm007/ALU-8-Bit-Adder
This is a basic project of Arithmetic Logic Unit that takes two input of 8 Bits each and undergoes 8 different operations and generates an output of 16 Bits
teekamkhandelwal/Uart_tx_main
Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate through digital pin 0, digital pin 1.
Venkaraddi7/Elevator_Controller
To implement the elevator controller, we used Verilog as HDL. The focus of our project was the implementation and verification of a controller for a basic elevator functionality. We also proposed a methodology that utilizes the SCAN algorithm to enhance the efficiency and reliability of the controller.
z1skgr/Tomasulo-BASED-processor
TOMASULO processor in VHDL implementation