/verilog-buses-implementations

Popular bus implementations in Verilog HDL

Primary LanguageVerilogMIT LicenseMIT

Verilog Buses Implementations

Popular bus implementations in Verilog HDL.

Project Official Language

The official language adopted by the project is Brazilian Portuguese; therefore, most of the documentation and commits are in this language.

Contribution

If you'd like to contribute to the project, please feel free to do so. The CONTRIBUTING.md file contains the necessary instructions.

License

This project is licensed under the CERN-OHL-P-2.0 license, which grants full freedom for use.