Jayanth-sharma

Jayanth-sharma's Stars

• abhisheknaiidu/awesome-github-profile-readme

  😎 A curated list of awesome GitHub Profile which updates in real time

  24.4k1601113.7k

• karpathy/nn-zero-to-hero

  Neural Networks: Zero to Hero

  Language:Jupyter Notebook11.7k287311.5k

• siliconcompiler/siliconcompiler

  Modular hardware build system

  Language:Python8562532085

• os-fpga/open-source-fpga-resource

  A list of resources related to the open-source FPGA projects

  38241143

• raulbehl/100DaysOfRTL

  100 Days of RTL

  Language:SystemVerilog32726596

• The-OpenROAD-Project/OpenROAD-flow-scripts

  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

  Language:Verilog32411371283

• RTimothyEdwards/open_pdks

  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

  Language:Python2872121285

• SparcLab/OpenSERDES

  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

  Language:Verilog13912729

• AbdelrahmanHassanMuhammed/Analog-IC-Design-Problems

  Solve one design problem each day for a month

  37204

• IamFlea/AdderCircuitGenerator

  This script generates and analyzes prefix tree adders.

  Language:Python37204

• shariethernet/Physical-Design-with-OpenLANE-using-SKY130-PDK

  This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified

  Language:Verilog37207

• jeshraghian/snn-accelerator

  Language:Verilog22111

• ishfaqahmed29/SerDes

  Verilog RTL Design

  Language:Verilog21206

• rohinthram/avsd_opamp

  Two Stage CMOS Operational Amplifier IP Design using Skywater 130nm Technology

  102

• Emad-H/Physical-Verification-using-SKY130

  Repository for VSD-IAT Workshop: Physical Verification using SKY130

  8105

• mjosaarinen/lwsha_isa

  [HISTORICAL] RISC-V ISA Extensions and Standard Hash Functions (contributions in 2020)

  Language:C8601

• pramitpal/msvsd_one_bit_adc

  VSD Research Program

  Language:Jupyter Notebook8111

• Ammar-10xe/RISCV-32I-Single-Cycle-Processor

  Implementation of RISCV32I Single Cycle Architecture consisting of six base instructions (R, I, B, S, J, U).

  Language:SystemVerilog6112

• akash-ambekar/VSD-5-DAYS-TCL-SCRIPTING-WORKSHOP

  TCL Workshop: From Introduction to Advanced Scripting Techniques in Design and Synthesis

  Language:Verilog412

• antonblanchard/OpenROAD

  OpenROAD's unified application implementing an RTL-to-GDS Flow

  Language:Verilog4301

• inderjit303/32-bit-SRAM-

  32-bit SRAM implementation in eSim using Skywater 130nm CMOS technology

  Language:Verilog410

• jargonized/tclprogrammingworkshop

  4130

• MadhuriKadam9/Phase-Locked-Loop-Design-in-Sky130nm

  Language:Verilog32

• ayushkashyap12/Physical-Verification-using-skywater-130nm

  Physical Verification using skywater 130nm

  2100

• bharath19-gs/AdvancedSynthesisandSTAwithDC

  2101

• drvasanthi/iiitb_cg

  Language:Verilog2101

• replica455/VLSI-Protocol

  communication and bus protocol

  Language:Verilog2101

• vyomasystems-lab/challenges-SoumitroV

  challenges-SoumitroV created by GitHub Classroom

  Language:Verilog201

• PavanDheeraj/Pavan_Mixed_Signal_Marathon

  Language:Verilog1100

• vyomasystems-lab/challenges-Jayanth-sharma

  challenges-Jayanth-sharma created by GitHub Classroom

  Language:Verilog100