Kenghsien

Kenghsien's Stars

• iperov/DeepFaceLab

  DeepFaceLab is the leading software for creating deepfakes.

  Language:Python46.7k1.1k1.3k10.4k

• jorgef/engineeringladders

  A framework for Engineering Managers

  7.9k14114557

• chipsalliance/chisel

  Chisel: A Modern Hardware Design Language

  Language:Scala3.9k1501k588

• cpq/bare-metal-programming-guide

  A bare metal programming guide (ARM microcontrollers)

  Language:C3.1k6821268

• yhzhang0128/egos-2000

  Envision a future where every student can read all the code of a teaching operating system.

  Language:C2.2k3212153

• gem5/gem5

  The official repository for the gem5 computer-system architecture simulator.

  Language:C++1.6k703181.2k

• riscv-mcu/e203_hbirdv2

  The Ultra-Low Power RISC-V Core

  Language:Verilog1.2k3519332

• aolofsson/oh

  Verilog library for ASIC and FPGA designers

  Language:Verilog1.2k9935284

• XUANTIE-RV/openc910

  OpenXuantie - OpenC910 Core

  Language:Verilog1.1k4627300

• ucb-bar/gemmini

  Berkeley's Spatial Array Generator

  Language:Scala77530182160

• ultraembedded/cores

  Various HDL (Verilog) IP Cores

  Language:Verilog683485207

• dawsonjon/fpu

  synthesiseable ieee 754 floating point library in verilog

  Language:Verilog5142325142

• raulbehl/100DaysOfRTL

  100 Days of RTL

  Language:SystemVerilog32326597

• XUANTIE-RV/openc906

  OpenXuantie - OpenC906 Core

  Language:Verilog313221494

• PacktPublishing/TinyML-Cookbook

  TinyML Cookbook, published by Packt

  Language:Jupyter Notebook23310665

• avakar/usbcorev

  A full-speed device-side USB peripheral core written in Verilog.

  Language:Verilog20618438

• WangXuan95/FPGA-CAN

  An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

  Language:Verilog2038463

• risclite/R8051

  8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

  Language:Verilog1618344

• WangXuan95/FPGA-DDR-SDRAM

  An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

  Language:Verilog1344228

• XUANTIE-RV/opene902

  OpenXuantie - OpenE902 Core

  Language:Verilog12912461

• XUANTIE-RV/opene906

  OpenXuantie - OpenE906 Core

  Language:Verilog12811664

• crypt-xie/XCryptCore

  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)

  Language:Verilog351014

• ptracton/AXI_BFM

  AXI4 BFM in Verilog

  Language:Verilog323018

• wimvanderbauwhede/OSH

  Code for the Operating Systems course

  Language:C305214

• cjacker/opensource-toolchain-8051

  Opensource toolchain for 8051 8-bit MCU

  Language:C27404

• muzafferkal/axi-bfm

  AXI3 Bus Functional Models (Initiator & Target)

  Language:SystemVerilog2615

• samy-maxvy/MAXVY_MIPI_I3C_Basic_Master_Controller_IP

  It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.

  Language:Verilog154

• wimvanderbauwhede/raspi3-tutorial

  Bare metal Raspberry Pi 3 tutorials

  Language:C9504

• gowgos5/aes-verilog

  RTL implementation of Advanced Encryption Standard (AES)

  Language:Verilog30

• sifive/block-i3cmaster-sifive

  This is a repository for Improved inter-integrated circuit master.

  Language:Scala1402