Emerging Computing Technology Laboratory at SJTU
A research group led by Prof. Weikang Qian from SJTU that focuses on emerging computing technologies, such as new computing paradigms and novel devices.
Shanghai Jiao Tong University, China
Pinned Repositories
ALSRAC
ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
DALS
DALS: Delay-Driven Approximate Logic Synthesis
EDA-Resource
Repository to store resources. Including benchmarking data, technology mapping libraries, etc.
GOMIL
GOMIL: Global Optimization of Multiplier by Integer Linear Programming
HEDALS
Highly efficient delay-driven approximate logic synthesis
MECALS
An approximate logic synthesis tool under the maximum error constraint
MinAC
MinAC: Minimal-Area Approximate Compressor Design Based on Exact Synthesis for Approximate Multipliers
MinSC
MinSC: An Exact Synthesis-Based Method for Minimal-AreaStochastic Circuits under Relaxed Error Bound
STOCA
STOCA: Stochastic Circuit Synthesis by Cube Assignment
VECBEE
VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis
Emerging Computing Technology Laboratory at SJTU's Repositories
SJTU-ECTL/ALSRAC
ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
SJTU-ECTL/VECBEE
VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis
SJTU-ECTL/GOMIL
GOMIL: Global Optimization of Multiplier by Integer Linear Programming
SJTU-ECTL/DALS
DALS: Delay-Driven Approximate Logic Synthesis
SJTU-ECTL/HEDALS
Highly efficient delay-driven approximate logic synthesis
SJTU-ECTL/MECALS
An approximate logic synthesis tool under the maximum error constraint
SJTU-ECTL/MinAC
MinAC: Minimal-Area Approximate Compressor Design Based on Exact Synthesis for Approximate Multipliers
SJTU-ECTL/MinSC
MinSC: An Exact Synthesis-Based Method for Minimal-AreaStochastic Circuits under Relaxed Error Bound
SJTU-ECTL/STOCA
STOCA: Stochastic Circuit Synthesis by Cube Assignment
SJTU-ECTL/BooleanNetwork
A simple data structure for boolean networks.
SJTU-ECTL/EDA-Resource
Repository to store resources. Including benchmarking data, technology mapping libraries, etc.
SJTU-ECTL/TFASC
TFASC: Target Function Approximation for Stochastic Circuit Minimization
SJTU-ECTL/simulator
A small simulator generates random inputs to `blif` circuit to simulator its behavior.
SJTU-ECTL/StaticTimingAnalysis
SJTU-ECTL/ALFANS-ER
Source codes for two algorithms in ALFANS paper that only involve error rate constraints.
SJTU-ECTL/ALFANS-ER-EM
Source codes for two algorithms in ALFANS paper that involve both error rate and error magnitues constraints.
SJTU-ECTL/SALODI
SALODI: Simultaneous Area and Latency Optimization for Stochastic Circuits by D Flip-flop Insertion
SJTU-ECTL/SCGen