This repository contains my Digital Logic Design course projects (Fall 2020) at University of Tehran.
- CA1 : Basic Switch and Gate Structure in Verilog
- CA2 : Basic Switch and Gate Structure in Verilog
- CA3 : Small-scale RT Level Components, Iterative Logic
- CA4 : Basic Memmory Structure, Latches and Flip-flops
- CA5 : Counters, Shifters, State Machines
- CA6 : RTL Complete Component Design