Pinned Repositories
4x4-Multiplier
Verilog HDL code for 4x4 multiplier
aes
C++ implementation of a 128-bit AES encryption/decryption tool.
Automatic-Food-Counter-using-Verilog-HDL-
A Verilog HDL Code for an automatic food cooker
Branch-Predictor-Project
Done as a part of CSE-614: Computer Architecture
Digital-Image-Watermarking-and-Its-FPGA-Implementation
My seminar topic as a part of BTech course in ECE. I would be first implementing different schemes of frequency domain watermark embedding and then implement the best one on FPGA.
DSA---CPP-and-Python
All impirtant Data Structures for coding in Python
DSP-Stuff
Useful MATLAB Codes
MIPS32
Basic implementation of MIPS32
NeuralNetworkOnFPGA
An initial proof of concept for neural network on FPGA
Verilog-HDL-Useful-Codes
Useful Verilog HDL Codes which can be used in multiple design systems.
Satjpatel's Repositories
Satjpatel/Verilog-HDL-Useful-Codes
Useful Verilog HDL Codes which can be used in multiple design systems.
Satjpatel/MIPS32
Basic implementation of MIPS32
Satjpatel/NeuralNetworkOnFPGA
An initial proof of concept for neural network on FPGA
Satjpatel/4x4-Multiplier
Verilog HDL code for 4x4 multiplier
Satjpatel/aes
C++ implementation of a 128-bit AES encryption/decryption tool.
Satjpatel/Automatic-Food-Counter-using-Verilog-HDL-
A Verilog HDL Code for an automatic food cooker
Satjpatel/Digital-Image-Watermarking-and-Its-FPGA-Implementation
My seminar topic as a part of BTech course in ECE. I would be first implementing different schemes of frequency domain watermark embedding and then implement the best one on FPGA.
Satjpatel/DSA---CPP-and-Python
All impirtant Data Structures for coding in Python
Satjpatel/DSP-Stuff
Useful MATLAB Codes
Satjpatel/Fp16_Arithmetic_modules
FP16_Arithmetic modules designed by Verilog and VHDL
Satjpatel/pdr
A repo for a Program and Data Representation university-level course
Satjpatel/Programmable-Logic-Block-for-Peripheral-Device-
A Verilog Code to mimic the functionality of the 8255 Interfacing Integrated Circuit
Satjpatel/RISCKY-Business
SV Implementation of RISC V ISA
Satjpatel/SoonChowkdi
A Tic Tac Toe game
Satjpatel/UVMPractice
UVM Practice on my own on a Small ALU
Satjpatel/VHDL-Useful-Codes
Over the course of my learning, I made some simple but useful VHDL codes, which can be helpful for bigger, more complex projects, and for those who are just beginning in the world of VHDL.
Satjpatel/zipcpu
A small, light weight, RISC CPU soft core
Satjpatel/Branch-Predictor-Project
Done as a part of CSE-614: Computer Architecture
Satjpatel/GURUKUL
Smart Class Projector Ecosystem - Swadeshi Microprocessor Challenge
Satjpatel/1stAttempt
Satjpatel/AsyncFIFO
An SV implementation of Asynchronous FIFO
Satjpatel/DSP-Project
RTL Design and Verification - with AXI-Lite Compatible Memory
Satjpatel/FIR-Filter-Design-in-SystemVerilog
A generic FIR filter implementation in System Verilog, and verified with Cocotb
Satjpatel/Implementation-and-Comparison-of-GHB-Based-Stride-Prefetcher-Feedback-Directed-Prefetching-and-a-C
Done as a part of coursework for ECEN-676 (Advanced Computer Architecture) at Texas A&M, Spring 2023
Satjpatel/Intelligent-Traffic-Light-Control-System-
A Verilog HDL Code for an Intelligent Traffic Light Control System ( Using State Machines)
Satjpatel/it-cert-automation-practice
Google IT Automation with Python Professional Certificate - Practice files
Satjpatel/Sat-sFirstAttempt
Satjpatel/Satjpatel
Config files for my GitHub profile.
Satjpatel/Technical-Articles
Contains all my written technical articles
Satjpatel/Tomasulo-s-Algorithm
A C++ Implementation of Tomasulo's Algorithm