Satjpatel

Satjpatel's Stars

• AMAI-GmbH/AI-Expert-Roadmap

  Roadmap to becoming an Artificial Intelligence Expert in 2022

  Language:JavaScript29.4k968642.5k

• lowRISC/ibex

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  Language:SystemVerilog1.4k99843560

• fastmachinelearning/hls4ml

  Machine learning on FPGAs using HLS

  Language:C++1.3k56425423

• drom/awesome-hdl

  Hardware Description Languages

  983622097

• eugene-tarassov/vivado-risc-v

  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

  Language:Tcl88335212198

• dgschwend/zynqnet

  Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"

  Language:HTML7487271297

• ben-marshall/awesome-open-hardware-verification

  A List of Free and Open Source Hardware Verification Tools and Frameworks

  50143548

• rajesh-s/computer-architecture-and-systems-resources

  A curated list of Computer Architecture and Systems resources

  47319253

• AnshMittal1811/MachineLearning-AI

  This repository contains all the work that I regularly did and studied from Medium blogs, several research papers, and other Repos (related/unrelated to the research papers).

  Language:Jupyter Notebook2036355

• skyzh/RISCV-Simulator

  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

  Language:C++1974119

• stnolting/neoTRNG

  🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

  Language:VHDL1756121

• mayurkubavat/UVM-Examples

  UVM examples and projects

  Language:SystemVerilog12314167

• AleksandarKostovic/SystemC-tutorial

  Brief SystemC getting started tutorial

  Language:C++874019

• digital-design-hq/Digital-Resources

  54305

• dpretet/cdc

  Repository gathering basic modules for CDC purpose

  Language:SystemVerilog51408

• caleb531/cache-simulator

  A processor cache simulator for the MIPS architecture

  Language:Python403018

• olofk/wb_intercon

  Wishbone interconnect utilities

  Language:Verilog387313

• georgeyhere/Toast-RV32i

  Pipelined RISC-V RV32I Core in Verilog

  Language:C36117

• rajesh-s/axi_cheatsheet

  A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)

  26412

• seifhelal/Cache-Simulator

  A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of references.

  Language:C++182010

• cache-sim/cache-sim

  cache simulator

  Language:C++821810

• snie2012/computer-architecture-projects

  Computer architecture related projects

  Language:C++8310

• 16oh4/LRU-Cache-Simulator

  A C++ simulation application of an LRU cache with VARIABLE cache size, block size, and associativity on a ~650000 memory address dump.

  Language:C++6103

• LC-John/Cache-Simulator

  PKU computer organization and architecture memory hierarchy simulator LAB

  Language:C++6202

• Swap76/Cache_Mapping_Technique

  Simulator for Direct, Associative, Set Associative Mapping Technique in Cache Allocation

  Language:C++5101

• Akashi96/Cpp-CacheSim

  A multi-threaded Cache Simulator implemented in C++11

  Language:C++3100

• rajesh-s/caws2020

  Computer Architecture Winter School 2020

  Language:C++3300

• Hong-Ming/Huffman-Codeing-IC

  Implemented 8-bit Huffman coding algorithm using SystemVerilog.

  Language:SystemVerilog1100

• rajesh-s/CoffeeBeforeArch.github.io

  120

• salvisumedh2396/salvisumedh2396.github.io

  Portfolio Page

  Language:HTML110