SkillSurf/systemverilog
SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow
SystemVerilogMIT
Stargazers
- 2phpHangZhou, ZheJiang,China
- AAIS2
- aitesam961aitesam961.github.io
- arturoEEZurich
- bimalka98Paraqum Technologies, LK (hybrid) | Sagence AI, USA (remote)
- ChalaniEkanayakeSri Lanka
- Charith47IFS
- DhananjayaSam
- eddygta17
- fartaha
- jerryw95
- Juanx65@AC3E-Synopsys, DINGS
- kana800@opensrilanka
- konosubakonoakuaIMP ⚜ BOSCH ⚜ CAEP ⚜ UESTC
- learningHWSWPUSAN NATIONAL UNIVERSITY
- leongseng123
- lochidev
- M2ohamadIBM Flash Systems
- maximtenna
- Michael-DV
- nipunaupekshaEADX
- NotLaith
- phsauterETH Zürich
- ptractonUSA
- ramithuhCMU
- SandaruJayawardanaThe University of Sydney
- Santhush95Sri Lanka
- shanyinshuiyue
- SLNimeshCreative Software
- Takikoi
- thuvasooriyaSri Lanka
- udithhaputhanthriStanford University
- xiapujuese1