VUnit testcases fail if the last character in a testcase name is a whitespace (VHDL)

[PossenigM]

Recently I noticed that a vunit testcase in a VHDL testbench will always fail if the name of it ends with a Whitespace. I attached a minimal example including a simple run.py script and a minimal testbench with two testcases. I tested this on two separate windows machines and got the same results on both pcs. Is this a bug in vunit or is something else wrong here?

MinimalExample.zip

from vunit import VUnit

# Create VUnit instance by parsing command line arguments
vu = VUnit.from_argv()

# Create library 'lib'
lib = vu.add_library("lib")

# Add all files ending in .vhd in current working directory to library
lib.add_source_files("*.vhd")

# Run vunit function
vu.main()

library vunit_lib;
context vunit_lib.vunit_context;

entity tb_Test is
  generic (runner_cfg : string);
end entity;

architecture tb of tb_Test is
begin
  main : process
  begin
    test_runner_setup(runner, runner_cfg);
    
    while test_suite loop

        if run("Test Fail ") then
            
            -- This Testcase fails because the name of the 
            -- Testcase ends in a whitespace
  
        elsif run("Test Pass") then
          
            -- This Testcase is successfull
            -- Note: There is no whitespace at the end
            
        end if;
      end loop;

    test_runner_cleanup(runner); -- Simulation ends here
  end process;
end architecture;