Data loss in AXI Slave VC
harry-commin-enclustra opened this issue · 0 comments
Problem
The axi_write_slave VC has std_logic_vector
ports, but internally stores data as integer
.
Converting to two-level logic is understandable in terms of execution speed. However, the conversion from 9-level to 2-level logic uses to_integer
, which presumes the data to be numeric:
record_input_data(input_data, aligned_address+j, to_integer(unsigned(wdata(8*j+7 downto 8*j))));
This means valid data is lost if it is (for example) padded with 'X':
Example: Write "X1010101"
--> Read "00000000"
.
Expected Behavior
If the port types were signed
or unsigned
then I think we could possibly argue that the current behavior is valid (because the input is an undefined numeric value). However, for non-numeric std_logic_vector
, there should be no dependency between the data bits.
Either of these behaviors could be considered valid (but the first is more conventional):
- Write
"X1010101"
--> Read"01010101"
. - Write
"X1010101"
--> Read"11010101"
.
Possible Solution
VHDL-2008 infamously implemented to_01
in a "less desirable" way, so I think standard practice is to define a more desirable function like this:
function to01(x : std_logic_vector) return std_logic_vector is
begin
return to_stdlogicvector(to_bitvector(x));
end;
which could be called like this:
record_input_data(input_data, aligned_address+j, to_integer(unsigned(to01(wdata(8*j+7 downto 8*j)))));