Xeenog

Xeenog's Stars

• kamranahmedse/developer-roadmap

  Interactive roadmaps, guides and other educational content to help developers grow in their careers.

  Language:TypeScript293k6.8k2.3k38.7k

• arduino/Arduino

  Arduino IDE 1.x

  Language:Java14.1k1.1k9.8k7k

• subbarayudu-j/TheAlgorithms-Python

  TheAlgorithms/Python

  Language:Python2.9k1396589

• orsanawwad/awesome-roadmaps

  View roadmaps about developer roles to help you learn

  1.9k963221

• unpingco/Python-for-Signal-Processing

  Notebooks for "Python for Signal Processing" book

  Language:Jupyter Notebook1.7k1397641

• olofk/serv

  SERV - The SErial RISC-V CPU

  Language:Verilog1.4k3758181

• The-OpenROAD-Project/OpenLane

  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  Language:Python1.3k59948368

• riscvarchive/riscv-cores-list

  RISC-V Cores, SoC platforms and SoCs

  824584202

• alexhagiopol/cracking-the-coding-interview

  :books: C++ and Python solutions with automated tests for Cracking the Coding Interview 6th Edition.

  Language:C++626301155

• cobanov/paul-graham-turkce

  Bu repo paulgraham.com adresindeki denemelerin Turkceye cevrilmis hallerinin yayinladigi gonulluluk ile buyuyen bir kaynaktir.

  284125133

• stnolting/neorv32-verilog

  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

  Language:Verilog579411

• jimmyg1997/Python-Digital-Signal-Processing-Basics

  📶 Python Scripts for the basics of Digital Signal Processing (DSP). Updating on a regular basis.

  Language:Jupyter Notebook22307

• zaman/19doc

  19 dokümanları

  16305

• rookiepeng/tx-line-calculator

  A transmission line calculator for RF/microwave engineers

  Language:Java72110

• dumbbanana/Industrial-automation

  Digital notes of Industrial Automation course

  4100

• Arsivnet/TodoList

  A todoList program written in C language.

  Language:C1100