a-vinod

a-vinod's Stars

• electron/electron

  :electron: Build cross-platform desktop apps with JavaScript, HTML, and CSS

  Language:C++115k2.8k20.4k15.7k

• ziglang/zig

  General-purpose programming language and toolchain for maintaining robust, optimal, and reusable software.

  Language:Zig36.2k37511.8k2.6k

• pola-rs/polars

  Dataframes powered by a multithreaded, vectorized query engine, written in Rust

  Language:Rust31.3k1689.5k2k

• karpathy/LLM101n

  LLM101n: Let's build a Storyteller

  30.9k2.6k01.7k

• drawdb-io/drawdb

  Free, simple, and intuitive online database diagram editor and SQL generator.

  Language:JavaScript23.4k1001621.6k

• keepassxreboot/keepassxc

  KeePassXC is a cross-platform community-driven port of the Windows application “Keepass Password Safe”.

  Language:C++21.8k2678.5k1.5k

• id-Software/DOOM

  DOOM Open Source Release

  Language:C++14.7k41802.4k

• blender/blender

  Official mirror of Blender

  Language:C++13.8k32002.1k

• rust-lang/cargo

  The Rust package manager

  Language:Rust13k1957.4k2.5k

• zephyrproject-rtos/zephyr

  Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

  Language:C11.2k41023.5k6.8k

• nasa/fprime

  F´ - A flight software and embedded systems framework

  Language:C++10.1k2611.1k1.3k

• apple/corenet

  CoreNet: A library for training deep neural networks

  Language:Jupyter Notebook7k6621543

• ratfactor/ziglings

  Learn the Zig programming language by fixing tiny broken programs.

  4.4k37153478

• westes/flex

  The Fast Lexical Analyzer - scanner generator for lexing in C and C++

  Language:C3.7k90330545

• enjoy-digital/litex

  Build your hardware, easily!

  Language:C3.1k99836584

• google/skywater-pdk

  Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

  Language:Python3k158274399

• steveicarus/iverilog

  Icarus Verilog

  Language:C++2.9k135731534

• verilator/verilator

  Verilator open-source SystemVerilog simulator and lint system

  Language:C++2.7k733.6k629

• chipsalliance/verible

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  Language:C++1.4k49968217

• ZigEmbeddedGroup/microzig

  Unified abstraction layer and HAL for several microcontrollers

  Language:Zig1.3k2463106

• omni-media/omniclip

  Open source video editing web application

  Language:TypeScript929111632

• OpenTimer/OpenTimer

  A High-performance Timing Analysis Tool for VLSI Systems

  Language:Verilog5804872144

• The-OpenROAD-Project/OpenSTA

  OpenSTA engine

  Language:C++42132172177

• chipsalliance/Surelog

  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

  Language:C++3782792068

• efabless/openlane2

  The next generation of OpenLane, rewritten from scratch with a modular architecture

  Language:Python2501327942

• jon77lee/JLee_LinearOptimizationBook

  Language:MATLAB1329015

• uwsampl/lakeroad

  FPGA synthesis tool powered by program synthesis

  Language:Racket3762586

• mole99/tiny-vga

  Tiny VGA Pmod board designed in KiCad

  15114

• wlneto/pathAnalyzer

  Language:Verilog8300

• NYU-MLDA/robust-pnr-time

  Implementation of ASPDAC 2021 paper: "Read your circuit: Leveraging word embedding to guide logic optimization"

  Language:Verilog5202