ben-marshall/verilog-vcd-parser

[Question] Is there any specific reason why VCDTime is a double instead unsigned long long?

mjc0608 opened this issue · 1 comments

mjc0608 commented

I noticed that VCDTime is declared as a double. However, all timestamps are added via add_timestamp, which is only called in VCDParser.ypp, and the argument is a TOK_DECIMAL_NUM, which is actually an integer. Is there any reason why VCDTime is a double instead of an integer?

ben-marshall commented

It's four years since I wrote that code, so I'm afraid I have no idea.
Cheers,
Ben