ben-marshall/verilog-vcd-parser

The latest version doesn't seem to recognize escaped identifiers.

RonxBulld opened this issue · 2 comments

RonxBulld commented

Consider this example:

$scope module top $end
  $var wire 1 (C \$procdff$4.Q[2] $end
  $var wire 1 (D \$procdff$4.Q[1] $end
  $var wire 1 (E \$procdff$4.Q[0] $end
  $var wire 1 (G \$procdff$4.D[2] $end
  $var wire 1 (H \$procdff$4.D[1] $end
  $var wire 1 (I \$procdff$4.D[0] $end
$upscope $end

It throws a yacc error:

line 2
 : syntax error, unexpected TOK_IDENTIFIER, expecting TOK_KW_END
bnkara commented

I encounter the same error on my end. Were you able to figure it out?

ben-marshall commented

Hi folks. Apologies for not responding sooner. The parser indeed doesn't support escaped identifiers, I guess I forgot to add it ages ago.

This project is currently archived as I have no time to support it. If you need a verilog parser, many other better projects have sprung up since I created this one. I currently point people at Verible as my usual choice. If you need a VCD parser, there are many other projects out there with better support.