Pinned Repositories
1st-CLaaS
Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
abc
ABC: System for Sequential Logic Synthesis and Formal Verification
acrn-hypervisor
Project ACRN hypervisor
ADMS
ADMS is a code generator for the Verilog-AMS language
Aes256
C++ library for AES 256 bit encryptation and decriptation
AHB2
AMBA AHB 2.0 VIP in SystemVerilog UVM
ahb3lite_interconnect
AHB3-Lite Interconnect
aiohttp
Asynchronous HTTP client/server framework for asyncio and Python
lbForth
Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.
TileLink
TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
brightclark's Repositories
brightclark/TileLink
TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
brightclark/ADMS
ADMS is a code generator for the Verilog-AMS language
brightclark/ahb3lite_interconnect
AHB3-Lite Interconnect
brightclark/asap7
brightclark/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
brightclark/bnn-fpga
Binarized Convolutional Neural Networks on Software-Programmable FPGAs
brightclark/coremark
CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
brightclark/DBT-RISE-RISCV
An instruction set simulator based on DBT-RISE implementing the RISC-V ISA
brightclark/DPU-PYNQ
DPU on PYNQ
brightclark/gapbs
GAP Benchmark Suite
brightclark/hwacha
Microarchitecture implementation of the decoupled vector-fetch accelerator
brightclark/libfuzzer-workshop
Repository for materials of "Modern fuzzing of C/C++ Projects" workshop.
brightclark/LM-RISCV-DV
An Open-Source Design and Verification Environment for RISC-V
brightclark/Lua-RTOS-ESP32
Lua RTOS for ESP32
brightclark/openwifi-hw
FPGA/hardware design of openwifi
brightclark/PicoBlaze-Library
The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).
brightclark/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
brightclark/pp4fpgas
Parallel Programming for FPGAs -- An open-source high-level synthesis book
brightclark/Q2RTX
NVIDIA’s implementation of RTX ray-tracing in Quake II
brightclark/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
brightclark/riscv-dv
Random instruction generator for RISC-V processor verification
brightclark/riscv-sodor
educational microarchitectures for risc-v isa
brightclark/riscv-vip
For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
brightclark/riscv-vp
RISC-V Virtual Prototype
brightclark/rocket-chip
Rocket Chip Generator
brightclark/ROCm
ROCm - Open Source Platform for HPC and Ultrascale GPU Computing
brightclark/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
brightclark/srsRAN
Open source SDR 4G/5G software suite from Software Radio Systems (SRS)
brightclark/sw
NVDLA SW
brightclark/threadx
Azure RTOS ThreadX is an advanced real-time operating system (RTOS) designed specifically for deeply embedded applications.