Pinned Repositories
1st-CLaaS
Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
abc
ABC: System for Sequential Logic Synthesis and Formal Verification
acrn-hypervisor
Project ACRN hypervisor
ADMS
ADMS is a code generator for the Verilog-AMS language
Aes256
C++ library for AES 256 bit encryptation and decriptation
AHB2
AMBA AHB 2.0 VIP in SystemVerilog UVM
ahb3lite_interconnect
AHB3-Lite Interconnect
aiohttp
Asynchronous HTTP client/server framework for asyncio and Python
lbForth
Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.
TileLink
TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
brightclark's Repositories
brightclark/babel
🐠 Babel is a compiler for writing next generation JavaScript.
brightclark/bluez-alsa
Bluetooth Audio ALSA Backend
brightclark/brew
🍺 The missing package manager for macOS (or Linux)
brightclark/common_cells
Common SV components
brightclark/core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
brightclark/devsim
TCAD Semiconductor Device Simulator
brightclark/drake
Model-based design and verification for robotics.
brightclark/edk2-test
Test infrastructure and test cases for EDK II based firmware
brightclark/grc
generic colouriser
brightclark/hdmi
Send video/audio over HDMI on an FPGA
brightclark/Kryon
FPGA,Verilog,Python
brightclark/linuxbrew-core
🍻🐧 Core formulae for the Homebrew package manager on Linux
brightclark/Mask_RCNN
Mask R-CNN for object detection and instance segmentation on Keras and TensorFlow
brightclark/mbed-os
Arm Mbed OS is a platform operating system designed for the internet of things
brightclark/moore
A hardware compiler based on LLHD.
brightclark/ncnn
ncnn is a high-performance neural network inference framework optimized for the mobile platform
brightclark/ninja
a small build system with a focus on speed
brightclark/oc-accel
OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
brightclark/OSVVM
Open Source VHDL Verification Methodology (OSVVM) Repository
brightclark/pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
brightclark/riscv-ovpsim-1
brightclark/scalacheck
Property-based testing for Scala
brightclark/sqlite
Unofficial git mirror of SQLite sources (see link for build instructions)
brightclark/symbiflow-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
brightclark/SymbiYosys
SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
brightclark/taskflow
Modern C++ Parallel Task Programming
brightclark/tvip-axi
AMBA AXI VIP
brightclark/utopia
A content-centric Ruby/Rack based web framework.
brightclark/vivado-library
brightclark/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research