Pinned Repositories
1st-CLaaS
Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
abc
ABC: System for Sequential Logic Synthesis and Formal Verification
acrn-hypervisor
Project ACRN hypervisor
ADMS
ADMS is a code generator for the Verilog-AMS language
Aes256
C++ library for AES 256 bit encryptation and decriptation
AHB2
AMBA AHB 2.0 VIP in SystemVerilog UVM
ahb3lite_interconnect
AHB3-Lite Interconnect
aiohttp
Asynchronous HTTP client/server framework for asyncio and Python
lbForth
Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.
TileLink
TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
brightclark's Repositories
brightclark/1st-CLaaS
Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
brightclark/benchmark
A microbenchmark support library
brightclark/blog
📚 专注前端与算法
brightclark/DDRCourses
DDR Courses collection for stepmania
brightclark/elixir
Elixir is a dynamic, functional language designed for building scalable and maintainable applications
brightclark/euvm
Embedded UVM (D Language port of IEEE UVM 1.0)
brightclark/flx
Fuzzy matching for Emacs ... a la Sublime Text.
brightclark/googletest
Googletest - Google Testing and Mocking Framework
brightclark/LDPC-codes
Software for Low Density Parity Check codes
brightclark/LxRunOffline
A full-featured utility for managing Windows Subsystem for Linux (WSL)
brightclark/MDL-SDK
NVIDIA Material Definition Language SDK
brightclark/melpa
Recipes and build machinery for the biggest Emacs package repo
brightclark/mockito
Most popular Mocking framework for unit tests written in Java
brightclark/myhdl
The MyHDL development repository
brightclark/nmigen
A refreshed Python toolbox for building complex digital hardware
brightclark/openofdm
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
brightclark/opentitan
OpenTitan: Open source silicon root of trust
brightclark/perl5
🐫The Perl language interpreter.
brightclark/Practical-UVM-Step-By-Step
This is the main repository for all the examples for the book Practical UVM
brightclark/RV12
RISC-V CPU Core
brightclark/s6_pcie_microblaze
PCI Express DIY hacking toolkit for Xilinx SP605
brightclark/seL4
The seL4 microkernel
brightclark/slang
SystemVerilog compiler and language services
brightclark/spacemacs
A community-driven Emacs distribution - The best editor is neither Emacs nor Vim, it's Emacs *and* Vim!
brightclark/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
brightclark/testng
TestNG testing framework
brightclark/tnoc
Network on Chip Implementation written in SytemVerilog
brightclark/travis-build
.travis.yml => build.sh converter
brightclark/vivado-boards
brightclark/warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.