cahz

cahz's Stars

• pulp-platform/culsans

  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol

  Language:C269

• antmicro/topwrap

  A Python package for generating HDL wrappers and top modules for HDL sources

  Language:Python182

• alexforencich/cocotbext-axi

  AXI interface modules for Cocotb

  Language:Python20968

• pulp-platform/FlooNoC

  A Fast, Low-Overhead On-chip Network

  Language:SystemVerilog11517

• lewiz-support/OmniXtend_RemoteAgent_RISC-V

  Language:Verilog71

• chipsalliance/OmnixtendEndpoint

  Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.

  Language:Bluespec134

• WerWolv/ImHex

  🔍 A Hex Editor for Reverse Engineers, Programmers and people who value their retinas when working at 3 AM.

  Language:C++42.7k1.9k

• lewiz-support/LMAC_CORE3

  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps

  Language:VHDL3618

• mgeeky/Penetration-Testing-Tools

  A collection of more than 170+ tools, scripts, cheatsheets and other loots that I've developed over years for Red Teaming/Pentesting/IT Security audits purposes.

  Language:PowerShell2.5k495

• openhwgroup/cva5

  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

  Language:SystemVerilog5514

• esa-tu-darmstadt/tapasco-riscv

  RISC-V soft-core PEs for TaPaSCo

  Language:Tcl1512

• scottbez1/smartknob

  Haptic input knob with software-defined endstops and virtual detents

  Language:C++19k1.1k

• HarisIqbal88/PlotNeuralNet

  Latex code for making neural networks diagrams

  Language:TeX21.8k2.8k

• riscv-ovpsim/imperas-riscv-tests

  Language:C15437

• Xilinx/open-nic

  AMD OpenNIC Project Overview

  Language:Shell21737

• yaqwsx/KiKit

  Automation tools for KiCAD

  Language:Python1.5k200

• fpgasystems/Vitis_with_100Gbps_TCP-IP

  100 Gbps TCP/IP stack for Vitis shells

  Language:C++17773

• B-Lang-org/bsc

  Bluespec Compiler (BSC)

  Language:Haskell927143

• abs-tudelft/fletcher

  Fletcher: A framework to integrate FPGA accelerators with Apache Arrow

  Language:VHDL21731

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.7k501

• kactus2/kactus2dev

  Kactus2 is a graphical EDA tool based on the IP-XACT standard.

  Language:C++19134

• bluespec/Piccolo

  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

  Language:Verilog30549

• esa-tu-darmstadt/tapasco

  The Task Parallel System Composer (TaPaSCo)

  Language:Verilog10424

• chipforge/StdCellLib

  Copyleftist's Standard Cell Library

  Language:TeX9621

• libresilicon/qtflow

  Free open source EDA tools

  Language:C++6419

• YosysHQ/nextpnr

  nextpnr portable FPGA place and route tool

  Language:C++1.3k240

• WRSC/tracking

  WRSC boat tracking system with web dashboard

  Language:Ruby137

• simonkohaut/stda-sailboat-simulator

  Language:Python86