chipsalliance/Cores-SweRV_fpga

Issues

• Mark this repo as deprecated or remove it

  #8 opened 2 years ago by olofk
  0

• Debug Module did not become active. dmcontrol=0x0

  #6 opened 4 years ago by kingstone1927
  1

• Cannot communicate through OpenOCD with Nexys A7

  #2 opened 5 years ago by monniaux
  13

• Routing issue when implement SweRV Core in Zedboard

  #7 opened 4 years ago by kingstone1927
  1

• Can not debug with openocd

  #5 opened 4 years ago by zhuzhizhan
  0

• Placement error

  #4 opened 4 years ago by monniaux
  3

• can't receive UART data from hello.c code

  #3 opened 5 years ago by damiencarrier
  1